---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 18:29:53 02/13/2013 -- Design Name: -- Module Name: four_alu - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity four_alu is Port ( A : in STD_LOGIC_VECTOR (3 downto 0); B : in STD_LOGIC_VECTOR (3 downto 0); K : in STD_LOGIC_VECTOR (1 downto 0); R : out STD_LOGIC_VECTOR (3 downto 0)); end four_alu; architecture Behavioral of four_alu is signal Reg1,Reg2,Reg3 : STD_LOGIC_VECTOR (3 downto 0) ; begin Reg1 <= A; Reg2 <= B; R <= Reg3; process (A,B,K) begin case K is when "00" => Reg3 <= Reg1 - Reg2 ; --when "01" => R <= A xor B; -- when "10" => R <= not A; -- when "11" => R <= SLL B; end case; end process; end Behavioral;