---------------------------------------------------------------------------------- -- Company: PSU -- Engineer: MICHAEL MIKULSKI -- -- Create Date: 14:36:53 10/11/2012 -- Design Name: -- Module Name: mm32x6RAM - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: 32 to 6 RAM -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mm32x6RAM is Port ( OE : in STD_LOGIC; CS : in STD_LOGIC; RW : in STD_LOGIC; A : in STD_LOGIC_VECTOR(4 downto 0); D : inout STD_LOGIC_VECTOR(5 downto 0)); end mm32x6RAM; architecture Struc of mm32x6RAM is COMPONENT mm5To32Decoder is Port ( A : in STD_LOGIC_VECTOR(4 downto 0); CSB : in STD_LOGIC; Z : out STD_LOGIC_VECTOR(31 downto 0)); end COMPONENT; COMPONENT mm1x6RAM is Port ( I : in STD_LOGIC_VECTOR(5 downto 0); W : in STD_LOGIC; R : in STD_LOGIC; S : in STD_LOGIC; D : out STD_LOGIC_VECTOR(5 downto 0)); end COMPONENT; COMPONENT mmInverter Port ( A : in STD_LOGIC; Z : out STD_LOGIC); end COMPONENT; COMPONENT mm3NOR Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; Z : out STD_LOGIC); end COMPONENT; COMPONENT mmOutputBuffer Port ( A : in STD_LOGIC_VECTOR(5 downto 0); OE : in STD_LOGIC; Z : out STD_LOGIC_VECTOR(5 downto 0)); end COMPONENT; SIGNAL N0 : STD_LOGIC; SIGNAL A1 : STD_LOGIC; SIGNAL RWN : STD_LOGIC; SIGNAL DA: STD_LOGIC_VECTOR(5 downto 0); SIGNAL DB: STD_LOGIC_VECTOR(5 downto 0); SIGNAL D0 : STD_LOGIC_VECTOR(31 downto 0); begin gate0 : mm5To32Decoder PORT MAP(A=>A,CSB=>CS,Z=>D0); gate1 : mmInverter PORT MAP(A=>RW,Z=>RWN); gate3 : mm3NOR PORT MAP(a=>OE,b=>CS,c=>RWN,z=>N0); gate4 : mmOutputBuffer PORT MAP(A=>DA,OE=>N0,Z=>D); gate5 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(31),D=>DA); gate6 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(30),D=>DA); gate7 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(29),D=>DA); gate8 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(28),D=>DA); gate9 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(27),D=>DA); gate10 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(26),D=>DA); gate11 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(25),D=>DA); gate12 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(24),D=>DA); gate13 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(23),D=>DA); gate14 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(22),D=>DA); gate15 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(21),D=>DA); gate16 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(20),D=>DA); gate17 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(19),D=>DA); gate18 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(18),D=>DA); gate19 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(17),D=>DA); gate20 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(16),D=>DA); gate21 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(15),D=>DA); gate22 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(14),D=>DA); gate23 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(13),D=>DA); gate24 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(12),D=>DA); gate25 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(11),D=>DA); gate26 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(10),D=>DA); gate27 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(9),D=>DA); gate28 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(8),D=>DA); gate29 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(7),D=>DA); gate30 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(6),D=>DA); gate31 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(5),D=>DA); gate32 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(4),D=>DA); gate33 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(3),D=>DA); gate34 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(2),D=>DA); gate35 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(1),D=>DA); gate36 : mm1x6RAM PORT MAP(I=>D,W=>RWN,R=>RW,S=>D0(0),D=>DA); end Struc;