---------------------------------------------------------------------------------- -- Company: PSU -- Engineer: Michael Mikulski -- -- Create Date: 00:21:41 10/04/2012 -- Design Name: -- Module Name: mmOutputBuffer - Behavioral -- Project Name: Project 4 -- Target Devices: -- Tool versions: -- Description: 6 bit Output Buffer -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mmOutputBuffer is Port ( B : in STD_LOGIC_VECTOR (5 downto 0); OE : in STD_LOGIC; D : out STD_LOGIC_VECTOR (5 downto 0)); end mmOutputBuffer; architecture Behavioral of mmOutputBuffer is COMPONENT mmInvBuf Port ( A : in STD_LOGIC; E : in STD_LOGIC; Q : out STD_LOGIC); end COMPONENT; begin gate1 : mmInvBuf PORT MAP(A=>B(5), E=>OE, Q=>D(5)); gate2 : mmInvBuf PORT MAP(A=>B(4), E=>OE, Q=>D(4)); gate3 : mmInvBuf PORT MAP(A=>B(3), E=>OE, Q=>D(3)); gate4 : mmInvBuf PORT MAP(A=>B(2), E=>OE, Q=>D(2)); gate5 : mmInvBuf PORT MAP(A=>B(1), E=>OE, Q=>D(1)); gate6 : mmInvBuf PORT MAP(A=>B(0), E=>OE, Q=>D(0)); end Behavioral;