---------------------------------------------------------------------------------- -- Company: PSU -- Engineer: Michael Mikulski -- -- Create Date: 00:21:41 10/04/2012 -- Design Name: -- Module Name: mm3NOR - Behavioral -- Project Name: Project 4 -- Target Devices: -- Tool versions: -- Description: 3 input NOR Gate -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mm3NOR is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; Z : out STD_LOGIC); end mm3NOR; architecture Behavioral of mm3NOR is begin Z<= not (A or B or C); end Behavioral;