---------------------------------------------------------------------------------- -- Company: PSU -- Engineer: Michael Mikulski -- -- Create Date: 20:12:39 08/30/2012 -- Design Name: -- Module Name: mm1by6RAM - Behavioral -- Project Name: Project 4 -- Target Devices: -- Tool versions: -- Description: RAM (1 X 6) -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity mm1by6RAM is Port ( I : in STD_LOGIC_VECTOR (5 downto 0); W : in STD_LOGIC; R : in STD_LOGIC; S : in STD_LOGIC; D : out STD_LOGIC_VECTOR (5 downto 0)); end mm1by6RAM; architecture Behavioral of mm1by6RAM is COMPONENT MMLatch Port ( D : in STD_LOGIC; W : in STD_LOGIC; Z : out STD_LOGIC); end COMPONENT; COMPONENT mmInvBuf Port ( A : in STD_LOGIC; E : in STD_LOGIC; Q : out STD_LOGIC); end COMPONENT; COMPONENT mmAND2 Port ( a : in STD_LOGIC; b : in STD_LOGIC; z : out STD_LOGIC); end COMPONENT; SIGNAL DL : STD_LOGIC_VECTOR (5 downto 0); SIGNAL A : STD_LOGIC_VECTOR (1 downto 0); SIGNAL IV : STD_LOGIC_VECTOR (5 downto 0); begin gate1 : MMLatch PORT MAP (D=>IV(0), W=>A(0), Z=>DL(0)); gate2 : MMLatch PORT MAP (D=>IV(1), W=>A(0), Z=>DL(1)); gate3 : MMLatch PORT MAP (D=>IV(2), W=>A(0), Z=>DL(2)); gate4 : MMLatch PORT MAP (D=>IV(3), W=>A(0), Z=>DL(3)); gate5 : MMLatch PORT MAP (D=>IV(4), W=>A(0), Z=>DL(4)); gate6 : MMLatch PORT MAP (D=>IV(5), W=>A(0), Z=>DL(5)); gate7 : mmAND2 PORT MAP (a=>W, b=>S, z=>A(0)); gate8 : mmAND2 PORT MAP (a=>R, b=>S, z=>A(1)); gate9 : mmInvBuf PORT MAP (a=>DL(0), E=>A(1), Q=>IV(0)); gate10 : mmInvBuf PORT MAP (a=>DL(1), E=>A(1), Q=>IV(0)); gate11 : mmInvBuf PORT MAP (a=>DL(2), E=>A(1), Q=>IV(0)); gate12 : mmInvBuf PORT MAP (a=>DL(3), E=>A(1), Q=>IV(0)); gate13 : mmInvBuf PORT MAP (a=>DL(4), E=>A(1), Q=>IV(0)); gate14 : mmInvBuf PORT MAP (a=>DL(5), E=>A(1), Q=>IV(0)); end Behavioral;