---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 23:57:27 05/15/2012 -- Design Name: -- Module Name: knbkj - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY dig_int IS GENERIC ( WIDTH : INTEGER := 4 ); PORT ( y : OUT STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0); x : IN STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0); clock : IN STD_LOGIC ); END dig_int; ARCHITECTURE trans OF dig_int IS SIGNAL z : STD_LOGIC_vector(WIDTH - 1 downto 0):="0000"; -- Declare intermediate signals for referenced outputs SIGNAL y_xhdl0 : STD_LOGIC_VECTOR(WIDTH - 1 DOWNTO 0); BEGIN -- Drive referenced outputs y <= y_xhdl0; PROCESS (x, z) BEGIN y_xhdl0 <= x + z; END PROCESS; PROCESS (clock) BEGIN IF (clock'EVENT AND clock = '1') THEN z <= y_xhdl0; END IF; END PROCESS; END trans;