`timescale 1ns / 1ps

module DDR3_Rst(
                  clk,
              Reset,
	cke
    );
	 
	 input clk;
	 output Reset;
	 output cke;
	 
	 reg Reset_i;
	 reg cke_i;
	 
 always@(clk)
 begin

 if(clk)
 begin
#0 Reset_i <= 1'b0;
#44 cke_i <= 1'b1;
 end
 
 else
 
 if(!clk)
 begin
#200655 Reset_i <= 1'b1;
  #189985 cke_i <= 1'b0;
#310162 cke_i <= 1'b1;
 end
 
 end
 

 assign Reset = Reset_i;
 assign cke = cke_i;
 

endmodule