library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity splitter is port ( CLK, RST: in STD_LOGIC; data_in: in STD_LOGIC_VECTOR(11 downto 0); START: in STD_LOGIC; RFD: in STD_LOGIC; -- watches for the empty shift register in the UART controller data_out: out STD_LOGIC_VECTOR(7 downto 0) := "00000000"; WR: out STD_LOGIC := '0' ); end splitter; architecture Behavioral of splitter is type State is (Init, Idle, Output); signal enDataCounter: STD_LOGIC := '0'; signal dataCounter: STD_LOGIC_VECTOR(2 downto 0) := "000"; signal next_state: State; signal current_state: State; begin sync_proc: process(CLK, RST) begin if (CLK'event and CLK = '1') then if (RST = '1') then current_state <= Init; else current_state <= next_state; end if; end if; end process; data_cnt_proc: process(RFD) begin if (RFD = '1' and RFD'event) then if (enDataCounter = '1') then case dataCounter is when "000" => data_out <= data_in(7 downto 0); when "001" => data_out <= "0000" & data_in(11 downto 8); when others => data_out <= "00000000"; end case; dataCounter <= dataCounter + '1'; end if; end if; end process; output_dec: process(current_state) begin if (current_state = Init) then enDataCounter <= '0'; dataCounter <= "000"; WR <= '0'; elsif (current_state = Idle) then enDataCounter <= '1'; WR <= '0'; elsif (current_state = Output) then WR <= '1'; end if; end process; next_dec: process(current_state, START, RFD, enDataCounter) begin case (current_state) is when Init => if (START = '1') then next_state <= Idle; end if; when Idle => if (enDataCounter = '1' and RFD = '1') then next_state <= Output; end if; when Output => if (enDataCounter = '1' and RFD = '0') then next_state <= Idle; elsif (enDataCounter = '0' and START = '0') then next_state <= Init; end if; end case; end process; end;