EmbDev.net

Forum: FPGA, VHDL & Verilog modelsim simulaiton


Author: KAYHAN ÇELİK (Company: gazi) (kayooo)
Posted on:
Attached files:

Rate this post
0 useful
not useful
hello
ı  made a fifo register with 9 bit wide and 8 bit deep

when ı make a simulation  wi or ri signal gives an error.
simulaiton says that  wi<= wi+1 or ri <=ri +1 dont be  make.
 but  my codes from the book . so there is no error in vhdl file.
but simulaiton dont work .
can any one help me please.

Author: P. K. (pek)
Posted on:

Rate this post
0 useful
not useful
KAYHAN Ç. wrote:
> when ı make a simulation  wi or ri signal gives an error.

What does the error message say?

Author: ulf (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello

There is not line, where wrinc goes high. So the "elsif (wrinc='1') 
never get's true.

Author: KAYHAN ÇELİK (Company: gazi) (kayooo)
Posted on:

Rate this post
0 useful
not useful
# ** Fatal: (vsim-3421) Value 8 for ri is out of range 0 to 7.
 Time: 23 ps  Iteration: 1  Process: /fifo_tb/dut/line__61 File: 
C:/Users/kayhan/modelsim/fifo.vhd
# Fatal error in Process line__61 at C:/Users/kayhan/modelsim/fifo.vhd 
line 69
#
# HDL call sequence:
# Stopped at C:/Users/kayhan/modelsim/fifo.vhd 69 Process line__61
#

this is the error messege.

Author: Svenska (Guest)
Posted on:

Rate this post
0 useful
not useful
A range value of 0 to 7 corresponds to three bits.
A range value of 0 to 255 corresponds to eight bits.

Author: P. K. (pek)
Posted on:

Rate this post
0 useful
not useful
KAYHAN Ç. wrote:
> # ** Fatal: (vsim-3421) Value 8 for ri is out of range 0 to 7.
>  Time: 23 ps  Iteration: 1  Process: /fifo_tb/dut/line__61 File:

I assume that your Modelsim does not do an automatic wrap-around of your 
limited integer.
I'd take an unsigned(2 downto 0) instead, this will be fine.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig