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Forum: FPGA, VHDL & Verilog HELP! Programming of DE2 Altera Board.


Author: Afkar Osman (Company: nanyang polytechnic) (afkarsosman)
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Hi,

Im back here asking yet another question. I'm done doing up my VHDL 
codes, and when i tried to upload the codes into my DE2 Altera 
Board(Cyclone II EP2C35F672C6N), it seems that it doesnt work even 
though it shows "SUCCESSFUL" upon uploading using Quartus II 12.1 
(64Bit). Tried using via JTAG and also Active Serial but still to no 
avail. Im not too sure if it is the coding that is wrong or simply the 
process of me programming the board.

If any of you can point out the mistakes I did, it would be greatly 
appreciated and I'll be thankful. Im still a beginner at VHDL so it is a 
little bit messy.

here are the codes, and also the attached file of what im currently 
facing. The codes shown here are my Main LCD, The Controller and also 
Clock Div is in the attached.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LCD_Main IS 
  PORT ( clk : IN std_logic;
      iRST_N : IN std_logic;
          SW : IN std_logic_vector(17 downto 0);
       reset : IN std_logic;
      switch : IN std_logic;
     switch2 : IN std_logic;
     
    LCD_DATA : OUT std_logic_vector(7 downto 0);
      LCD_RW : OUT std_logic;
      LCD_ON : OUT std_logic;
    LCD_BLON : OUT std_logic;
      LCD_RS : OUT std_logic;
      LCD_EN : OUT std_logic:='0' 
       );
END LCD_Main;

ARCHITECTURE LCDBody of LCD_Main is
  
  CONSTANT LCD_INITIAL:std_logic_vector(7 downto 0):="00000000";
  CONSTANT LCD_LINE1:std_logic_vector(7 downto 0):= "00000100";
  CONSTANT LCD_CH_LINE:std_logic_vector(7 downto 0):=LCD_LINE1+16;
  CONSTANT LCD_LINE2:std_logic_vector(7 downto 0):=LCD_LINE1+16+1;
  CONSTANT LUT_SIZE:std_logic_vector(7 downto 0):=(LCD_LINE2+50)+1;
  
  SIGNAL LUT_DATA:std_logic_vector (11 downto 0):=x"000";--In hex    
--  SIGNAL count2 : integer range 0 to 65535 := 0;
  SIGNAL LUT_INDEX:std_logic_vector(7 downto 0):="00000000";
  SIGNAL mLCD_DONE:std_logic:='0';
 -- SIGNAL mLCD_ST:std_logic_vector(5 downto 0):="000000";
  SIGNAL mLCD_ST:std_logic_vector(1 downto 0):="00";
  SIGNAL mDLY:std_logic_vector(27 downto 0):=x"0000000";--In hex
  SIGNAL mLCD_Start:std_logic:='0';
  SIGNAL mLCD_DATA:std_logic_vector(7 downto 0):="00000000";
  SIGNAL mLCD_RS:std_logic:='0';
  SIGNAL sclk:std_logic:='0';
  SIGNAL startcount : integer range 0 to 1:=0;
  SIGNAL D1,D2,D3,D4,D5,D6 : std_logic_vector (11 downto 0):=x"130";
--  SIGNAL D1,D2,D3,D4,D5,D6 : std_logic_vector (11 downto 0);

  COMPONENT LCD_controller IS
       PORT( iCLK,iRS,iRST_N,istart : IN std_logic;
                              iDATA : IN std_logic_vector(7 downto 0);
                              oDone : OUT std_logic;
                           LCD_DATA : OUT std_logic_vector(7 downto 0);
                             LCD_RW : OUT std_logic;
                             LCD_RS : OUT std_logic;
                             LCD_EN : OUT std_logic
           );
  END COMPONENT LCD_controller;
  
  COMPONENT clk_div IS
         PORT ( iCLK: IN std_logic;
                sclk: OUT std_logic
               );
  END COMPONENT clk_div; 
  
  BEGIN      
       U0:LCD_controller 
       PORT MAP(
                  iCLK => clk,
                   iRS => mLCD_RS,
                iRST_N => iRST_N,
                istart => mLCD_START,
                 iDATA => mLCD_DATA,
                 oDone => mLCD_DONE,
              LCD_DATA => LCD_DATA,
                LCD_RW => LCD_RW,
                LCD_RS => LCD_RS,
                LCD_EN => LCD_EN
                );
                
        U1:clk_div 
        PORT MAP( iCLK => clk,
                  sclk => sclk
                 ); 
                       
    LCD_ON <= '1';
    LCD_BLON <= '1';
    
always : process(clk,reset,sclk)
    Begin
      IF(SW(0)='1')THEN
      D1 <= x"132";
      ELSIF(SW(1)='1')THEN
      D2 <= x"133";
      END IF;
      
      IF(reset = '1')THEN
          LUT_INDEX <= "00000000";
          --mLCD_ST <= "000000";
          mLCD_ST <= "00";
          --mDLY <= x"0000000";
          mLCD_DATA <= "00000000";
          mLCD_START <= '0';
          mLCD_RS <= '0';
          
          startcount <= 0;
          D1 <= x"130";
          D2 <= x"130";
          D3 <= x"130";
          D4 <= x"130";
          D5 <= x"130";
          D6 <= x"130";
      
----------LCD Line 1--------------
        
          
      ELSIF(rising_edge(clk))THEN
        startcount <= startcount + 1;
          IF (startcount = 1)THEN
            
            IF(LUT_INDEX < LUT_SIZE)THEN
              case mLCD_ST is
                  when "00" => mLCD_DATA <= LUT_DATA(7 downto 0);
                          mLCD_RS   <= LUT_DATA(8);
                          mLCD_START<= '1';
                          mLCD_ST   <= "01";
              
                  when "01" => IF(mLCD_DONE = '1') THEN
                          mLCD_START <= '0';
                          mLCD_ST    <= "10";
                         END IF;
                          
                  when "10" => IF(switch = '1')THEN
                          IF(LUT_DATA = x"080")THEN
                            mLCD_ST <= "11";
                          END IF;
                         END IF; 
                            
                  when "11" => LUT_INDEX <= LUT_INDEX + 1;
                         mLCD_ST   <= "00";
              end case;
            ELSE
                IF(sclk = '1')THEN
                  LUT_INDEX <= LCD_INITIAL;
                END IF;
            END IF;
            
          END IF;
      END IF;
END PROCESS always;    



----READING OF LCD COMMAND----
check:process(LUT_INDEX)
      begin

  case LUT_INDEX is  
   when LCD_INITIAL+0=>LUT_DATA<=(x"030");
   when LCD_INITIAL+1=>LUT_DATA<=(x"00C");         
   when LCD_INITIAL+2=>LUT_DATA<=(x"001");          
   when LCD_INITIAL+3=>LUT_DATA<=(x"006");           
   when LCD_INITIAL+4=>LUT_DATA<=(x"080");
   
   

   
   when LCD_LINE1 + 1 => LUT_DATA<=(x"130");
   when LCD_LINE1 + 2 => LUT_DATA<=(x"130");
   when LCD_LINE1 + 3 => LUT_DATA<=(x"130");
   when LCD_LINE1 + 4 => LUT_DATA<=(D6);
   when LCD_LINE1 + 5 => LUT_DATA<=(D5);
   when LCD_LINE1 + 6 => LUT_DATA<=(x"13a");
   when LCD_LINE1 + 7 => LUT_DATA<=(D4);
   when LCD_LINE1 + 8 => LUT_DATA<=(D3);
   when LCD_LINE1 + 9 => LUT_DATA<=(x"13a");
   when LCD_LINE1 + 10=> LUT_DATA<=(D2);
   when LCD_LINE1 + 11=> LUT_DATA<=(D1);
--   when LCD_LINE1 + 12=> LUT_DATA<=(x"130");
--   when LCD_LINE1 + 13=> LUT_DATA<=(x"130");
--   when LCD_LINE1 + 14=> LUT_DATA<=(x"130");
--   when LCD_LINE1 + 15=> LUT_DATA<=(x"130");
--   when LCD_LINE1 + 16=> LUT_DATA<=(x"130");  
   when others => LUT_DATA <= (x"000");

   end case;   

  end process check; 
end LCDBody;

Author: ui (Guest)
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Usually the upload process works if there is the green "successful" 
message.
I don't read the code because I think you should simulate and test it 
with modelsim, so the answer if it works can only be given by yourself!

Its often a good idea to start with a very generic example (just a 
counter and a blinking led) to test the toolchain and see if you
- flash the right binary
- the upload process works

Author: Duke Scarring (Guest)
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Did you set the correct pins in your design?
Youtube-Video "Programming Altera FPGAs on the DE0, DE1 or DE2 (Sec 4-4D )"

Did you simulate your design?
My approach is: first simulate, 2nd synthesize

I stronly suggest: avoid ieee.std_logic_unsigned.all, use 
ieee.numeric_std.all instead.

Why did you have two reset signals (iRST_N and reset)?

I attached a small testbench. The simulation stops with out-of-range 
error:
# ** Fatal: (vsim-3421) Value 2 is out of range 0 to 1.
#    Time: 30 ns  Iteration: 0  Process: /lcd_main_testbench/dut/always File: LCD_Main.vhd
# Fatal error in Process always at LCD_Main.vhd line 114

Duke

Author: Afkar Osman (Company: nanyang polytechnic) (afkarsosman)
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Hi Duke!

thank you for taking the time to test it out for me, it is greatly 
appreciated! I'll go and review again my codes and will test it out with 
your testbench! Thank you again Duke!

regards,
Afkar O.

Author: Lothar Miller (lkmiller) (Moderator)
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This ist is an wrong sensitivity list, leading to a wrong simulation:
always : process(clk,reset,sclk)
    Begin
      IF(SW(0)='1')THEN
      D1 <= x"132";
      ELSIF(SW(1)='1')THEN
      D2 <= x"133";
      END IF;

      IF(reset = '1')THEN
          LUT_INDEX <= "00000000";
          --mLCD_ST <= "000000";
          mLCD_ST <= "00";
      :
SW is missing and sclk is not needed therein.

Afkar O. wrote:
> it seems that it doesnt work
Your startcount prohibits any proper function of this this design. This 
counter is not limited just by the definition "rango 0 to 1". You must 
handle the overflow yourself.
Here this code results in the curious behaviour that startcount is 
synthesized to 1 bit that toggles every clock cycle due to "startcount 
<= startcount+1".

As Duke said already: you MUST run a simulation. The simulator is the 
debugger of a FPGA design.

: Edited by Moderator

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