EmbDev.net

Forum: FPGA, VHDL & Verilog Measuring of time of execution on ZED board, in Vivado


Author: Sai Shashi (Company: sssihl) (shashidhar)
Posted on:

Rate this post
0 useful
not useful
Hello there,

I have developed an image processing algorithm using the system 
generator and Generated the HDL netlist. Now i need to send the image 
file to the Verilog code generated, and compute the output and measure 
the time.

Can anyone please help me in understanding how i should, input the 
image, get the output and then measure the time of execution on ZED 
board?

Thanks in advance.

Author: Duke Scarring (Guest)
Posted on:

Rate this post
0 useful
not useful
Sai S. wrote:
> Can anyone please help me in understanding how i should, input the
> image, get the output and then measure the time of execution on ZED
> board?
How to send your image and grab your output depend strongly on your 
system.

I can help with time measurements: I often use an LED output with an 
oscilloscope for that. Switch the LED on when the function is starting, 
switch it off, when the function is ready. Digital oscilloscopes have 
measurements functions which can display the pulse with directly.

Duke

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig