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Forum: FPGA, VHDL & Verilog vhdl code for ram does not simulate


Author: SIDHANT SAXENA (Guest)
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I'm a beginner in VHDL and I've been trying to simulate this 
code(attached) with the following test bench and there are no results
can someone plz tell me what i have been doing wrong or what shoul i 
do??

TESTBENCH
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;

entity ram_tb is
end ram_tb;

architecture behavioral of ram_tb is

component ram
port( clk,wr,rd,enable,reset: in std_logic;
address: in std_logic_vector(3 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0)
);
end component;

signal wr,rd,enable,clk,reset: std_logic;
signal address: std_logic_vector(3 downto 0);
signal data_in,data_out: std_logic_vector(7 downto 0);

begin
uut: ram port map 
(wr=>wr,rd=>rd,enable=>enable,reset=>reset,clk=>clk,address=>address,dat 
a_in=>data_in,data_out=>data_out);

process
begin

clk<= '1';
wait for 5 ns;
clk<= '0';
wait for 5 ns;
end process;

process
begin

reset<= '1';
wait for 10 ns;

reset<= '0';
enable<= '1';
wr<= '1';
data_in<= 
("10000000","01000000","00100000","00010000","00001000","00000100","0000 
0010","00000001","10000001",
"01000010","00100100","00011000","11000011","00111100","10101010","01010 
101");
wait for 100 ns;

rd<= '1';
address<= "0000";
wait for 10 ns;
address<= "0001";
wait for 10 ns;
address<= "0010";
wait for 10 ns;
address<= "0011";
wait for 10 ns;
address<= "0100";
wait for 10 ns;
address<= "0101";
wait for 10 ns;
address<= "0110";
wait for 10 ns;
address<= "0111";
wait for 10 ns;
address<= "1000";
wait for 10 ns;
address<= "1001";
wait for 10 ns;
address<= "1010";
wait for 10 ns;
address<= "1011";
wait for 10 ns;
address<= "1100";
wait for 10 ns;
address<= "1101";
wait for 10 ns;
address<= "1110";
wait for 10 ns;
address<= "1111";
wait;

end process;
end behavioral;

Author: VHDL hotline (Guest)
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SIDHANT SAXENA wrote:
> what i have been doing wrong

You gave no sufficient description of your problem.

SIDHANT SAXENA wrote:
> what shoul i
> do

Describe what you expect and what happens.

First try to use a low active reset in testbench as your design also 
does.

Author: Klakx (Guest)
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Do you get a syntax error? Because thats how you get a syntax error.

data_in: in std_logic_vector(7 downto 0);

data_in<=
("10000000","01000000","00100000","00010000","00001000","00000100","0000
0010","00000001","10000001",
"01000010","00100100","00011000","11000011","00111100","10101010","01010
101");

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