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Forum: FPGA, VHDL & Verilog How to perform division of two Q15 values in Verilog , with out using '/' (division) Operator?


Author: Mog4kor Kumar (Company: student) (mohankotgire) Flattr this
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Hello,

As division operation (/) is expensive in case of FPGA ? Is it possible 
to perform division of two Q15 format numbers with basic shift 
operations?

Could someone help me by providing some example?

Thanks in advance!

Author: Charles Gardiner (Company: Ingenieurbuero Gardiner) (cfgardiner)
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The solution is outlined in most standard text-books on logic design. In 
"Computer Organisation and Design" from Patterson and Hennessy it's 
around page 260 (2nd Edition).

It's not that difficult really. My solution derived from the description 
in the text runs to 120 lines of VHDL code, including empty lines, two 
processes and a function to make things more readable.

Now that's something for free, isn't it ;) And I'd never forgive myself 
for just throwing code at you providing a solution you don't understand 
....

Author: Lothar Miller (lkmiller) (Moderator)
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Mohan K. wrote:
> As division operation (/) is expensive in case of FPGA ?
Yes, it is. It results in a big and slow combinatorial divider. Simply 
try it. And have a look for the RTL schematics.

> Is it possible  to perform division of two Q15 format numbers
> with basic shift  operations?
Yes.
And it's fairly simple...

Author: Mog4kor Kumar (Company: student) (mohankotgire) Flattr this
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Hello Mr.Charles Gardiner ,

Thanks for the reference , I found a detailed explanation in the 
mentioned book. Now i need to implement the same in Verilog to divide 
two numbers (X[15], Y[15]) . If you already have some Verilog code 
,which performs division operation of any two binary numbers with shift 
operation . Could you share it with me (only if you already have)? I 
dont have any problem if the code doesn't have comments ;). It will 
reduce my effort a lot :)

Author: Charles Gardiner (Company: Ingenieurbuero Gardiner) (cfgardiner)
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> Could you share it with me (only if you already have)? I
> dont have any problem if the code doesn't have comments ;). It will
> reduce my effort a lot :)

Not meaning to hurt your feelings, but you're beginning to sound a bit 
like my granddaughter when she doesn't want to do things herself even 
though she often could. She has the same perseverance as well ...

Sorry, I don't do Verilog unless you pay me. It feels like trying to 
carve a statue with a screwdriver. I need compensation for that. 
SystemVerilog is a different matter.

Back to the point, if you really want code you don't understand, I can 
certainly help you there. The attachment is the obfuscated solution for 
unsigned 32-bit dividend/divisor in VHDL, but it's not as useless for 
your task as it might seem at first. For a 16-bit solution, you probably 
just have to change the vector widths from 6 downto 0 to 5 downto 0

You could
1) write a Verilog wrapper around it and instantiate that in a mixed 
language environment

2) synthesise it and work out the code from the logic generated. Maybe 
you're a guy who understands schematics better than text books.

3) With some FPGA tools you can even write out a verilog netlist, which 
will give you what you want, just hope your tutor will accept it.

If your synthesis tool is complaining about unconstrained ports, just 
set the vectors on the top-level divider_uu to (31 downto 0) or (15 
downto 0)

Author: Mog4kor Kumar (Company: student) (mohankotgire) Flattr this
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Charles G. wrote:
>
> Not meaning to hurt your feelings, but you're beginning to sound a bit
> like my granddaughter when she doesn't want to do things herself even
> though she often could. She has the same perseverance as well ...
>
No you didn't hurt me, as of course I could do it by myself with the 
help of reference you provided , But tried to escape from that even( MY 
Bad :( ).
 .Hahaha..may be you are right I started sounding like your grand 
daughter.

> Sorry, I don't do Verilog unless you pay me. It feels like trying to
> carve a statue with a screwdriver. I need compensation for that.
> SystemVerilog is a different matter.
>
May be I could have paid for that , but i wont learn verilog if I do so 
.Nervelessness , the code you provided is perfect. It helped me a bit to 
correct my implemented code. Thanks for that :). I could see 11 people 
already downloaded your code(many like me trying to  escape from putting 
effort ;) )

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