EmbDev.net

Forum: FPGA, VHDL & Verilog Signals are not getting U value


von Tammy (Guest)


Rate this post
useful
not useful
I’m implementing IDEA algorithm using VHDL, I have a problem in my 
keygenerator module, when I run the simulator I get values U in all of 
the signals even though I assign other values to them.
1
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
5
-- Create Date:    17:00:11 12/06/2012 
6
-- Design Name: 
7
-- Module Name:    key_generator - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
13
-- Dependencies: 
14
--
15
-- Revision: 
16
-- Revision 0.01 - File Created
17
-- Additional Comments: 
18
--
19
----------------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.ALL;
22
23
-- Uncomment the following library declaration if using
24
-- arithmetic functions with Signed or Unsigned values
25
--use IEEE.NUMERIC_STD.ALL;
26
27
-- Uncomment the following library declaration if instantiating
28
-- any Xilinx primitives in this code.
29
--library UNISIM;
30
--use UNISIM.VComponents.all;
31
32
entity keygenerator is
33
    Port ( round : in  STD_LOGIC_VECTOR (3 downto 0);
34
           key : in  STD_LOGIC_VECTOR (127 downto 0);
35
           keyout1 : out  STD_LOGIC_VECTOR (15 downto 0);
36
           keyout2 : out  STD_LOGIC_VECTOR (15 downto 0);
37
           keyout3 : out  STD_LOGIC_VECTOR (15 downto 0);
38
           keyout4 : out  STD_LOGIC_VECTOR (15 downto 0);
39
           keyout5 : out  STD_LOGIC_VECTOR (15 downto 0);
40
           keyout6 : out  STD_LOGIC_VECTOR (15 downto 0));
41
end keygenerator;
42
43
architecture Behavioral of keygenerator is
44
45
  SIGNAL key0 : std_logic_vector (127 downto 0);
46
  SIGNAL key1 : std_logic_vector (127 downto 0);
47
  SIGNAL key2 : std_logic_vector (127 downto 0);
48
  SIGNAL key3 : std_logic_vector (127 downto 0);
49
  SIGNAL key4 : std_logic_vector (127 downto 0);
50
  SIGNAL key5 : std_logic_vector (127 downto 0);
51
  SIGNAL key6 : std_logic_vector (95 downto 0);
52
  
53
  signal output : std_logic_vector (95 downto 0);
54
55
  
56
begin
57
58
  process (round, key)
59
    
60
  begin
61
    key0 <= key;
62
    key1 <= key0(102 downto 0) & key0(127 downto 103);
63
    key2 <= key1(102 downto 0) & key1(127 downto 103);
64
    key3 <= key2(102 downto 0) & key2(127 downto 103);
65
    key4 <= key3(102 downto 0) & key3(127 downto 103);
66
    key5 <= key4(102 downto 0) & key4(127 downto 103);
67
    key6 <= key5(102 downto 7); 
68
  
69
    case round is
70
      when "0000" => output <= key0(127 downto 32);
71
      when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);
72
      when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);
73
      when "0011" => output <= key2(95 downto 0);
74
      when "0100" => output <= key3(127 downto 32);
75
      when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);
76
      when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);
77
      when "0111" => output <= key5(95 downto 0);
78
      when "1000" => output <= key6;
79
      when others => output <= (others => 'X');
80
    end case;
81
    
82
  end process;
83
84
  keyout6 <= output(15 downto 0);
85
  keyout5 <= output(31 downto 16);
86
  keyout4 <= output(47 downto 32);
87
  keyout3 <= output(63 downto 48);
88
  keyout2 <= output(79 downto 64);
89
  keyout1 <= output(95 downto 80);
90
  
91
end Behavioral;

That's my testbench:
1
--------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer:
4
--
5
-- Create Date:   18:59:37 12/12/2016
6
-- Design Name:   
7
-- Module Name:   /nfs/TUEIEDA/LabHDL/2016w/ga92xuv/submit/rcs1/tb_keygenerator.vhd
8
-- Project Name:  idea_rcs1
9
-- Target Device:  
10
-- Tool versions:  
11
-- Description:   
12
-- 
13
-- VHDL Test Bench Created by ISE for module: keygenerator
14
-- 
15
-- Dependencies:
16
-- 
17
-- Revision:
18
-- Revision 0.01 - File Created
19
-- Additional Comments:
20
--
21
-- Notes: 
22
-- This testbench has been automatically generated using types std_logic and
23
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
24
-- that these types always be used for the top-level I/O of a design in order
25
-- to guarantee that the testbench will bind correctly to the post-implementation 
26
-- simulation model.
27
--------------------------------------------------------------------------------
28
LIBRARY ieee;
29
USE ieee.std_logic_1164.ALL;
30
 
31
-- Uncomment the following library declaration if using
32
-- arithmetic functions with Signed or Unsigned values
33
--USE ieee.numeric_std.ALL;
34
 
35
ENTITY tb_keygenerator IS
36
END tb_keygenerator;
37
 
38
ARCHITECTURE behavior OF tb_keygenerator IS 
39
 
40
    -- Component Declaration for the Unit Under Test (UUT)
41
 
42
    COMPONENT keygenerator
43
    PORT(
44
         round : IN  std_logic_vector(3 downto 0);
45
         key : IN  std_logic_vector(127 downto 0);
46
         keyout1 : OUT  std_logic_vector(15 downto 0);
47
         keyout2 : OUT  std_logic_vector(15 downto 0);
48
         keyout3 : OUT  std_logic_vector(15 downto 0);
49
         keyout4 : OUT  std_logic_vector(15 downto 0);
50
         keyout5 : OUT  std_logic_vector(15 downto 0);
51
         keyout6 : OUT  std_logic_vector(15 downto 0)
52
        );
53
    END COMPONENT;
54
    
55
56
   --Inputs
57
   signal round : std_logic_vector(3 downto 0) := (others => '0');
58
   signal key : std_logic_vector(127 downto 0) := (others => '0');
59
60
   --Outputs
61
   signal out1 : std_logic_vector(15 downto 0);
62
   signal out2 : std_logic_vector(15 downto 0);
63
   signal out3 : std_logic_vector(15 downto 0);
64
   signal out4 : std_logic_vector(15 downto 0);
65
   signal out5 : std_logic_vector(15 downto 0);
66
   signal out6 : std_logic_vector(15 downto 0);
67
   -- No clocks detected in port list. Replace <clock> below with 
68
   -- appropriate port name 
69
 
70
   constant I_period : time := 10 ns;
71
 
72
BEGIN
73
 
74
  -- Instantiate the Unit Under Test (UUT)
75
   uut: keygenerator PORT MAP (
76
          round => round,
77
          key => key,
78
          keyout1 => out1,
79
          keyout2 => out2,
80
          keyout3 => out3,
81
          keyout4 => out4,
82
          keyout5 => out5,
83
          keyout6 => out6
84
        );
85
86
   -- Clock process definitions
87
   I_process :process
88
   begin
89
    key <= X"12345678912345678912345678912345";
90
    round <="1100";
91
    wait for I_period/2;
92
    key <= X"12345678912345678912345678912345";
93
    round <="1001";
94
    wait for I_period/2;
95
   end process;
96
97
98
END;

von Achim S. (Guest)


Rate this post
useful
not useful
The assignment to a signal inside a process is not executed at the line 
where the assignment is written but at the end of the process. So if you 
write

    key0 <= key;

inside a process, then key0 still holds its former value (i.e. "U"s) 
until the process is at its end. Therefor in the next line

       key1 <= key0(102 downto 0) & key0(127 downto 103);

you assign "U"s to key1 ....

Things would look different ...
- if you would make the assignments to key0 .. key6 outside of the 
process
- if you would extend the sensitivity list of your process
- if you would use variables for key0 .. key6 instead of signals (this 
is a good example to understand the differences between signals and 
variables)
- if you would use a process which is controlled by a clock edge

Is your key-generator really intended to run without any clock?

von Tammy (Guest)


Rate this post
useful
not useful
This is an assignment and we are supposed to run it without any clock.
I used variables instead of signals and I still get the same error.
That's my updated code:
1
library IEEE;
2
use IEEE.STD_LOGIC_1164.ALL;
3
4
-- Uncomment the following library declaration if using
5
-- arithmetic functions with Signed or Unsigned values
6
--use IEEE.NUMERIC_STD.ALL;
7
8
-- Uncomment the following library declaration if instantiating
9
-- any Xilinx primitives in this code.
10
--library UNISIM;
11
--use UNISIM.VComponents.all;
12
13
entity keygenerator is
14
    Port ( round : in  STD_LOGIC_VECTOR (3 downto 0);
15
           key : in  STD_LOGIC_VECTOR (127 downto 0);
16
           keyout1 : out  STD_LOGIC_VECTOR (15 downto 0);
17
           keyout2 : out  STD_LOGIC_VECTOR (15 downto 0);
18
           keyout3 : out  STD_LOGIC_VECTOR (15 downto 0);
19
           keyout4 : out  STD_LOGIC_VECTOR (15 downto 0);
20
           keyout5 : out  STD_LOGIC_VECTOR (15 downto 0);
21
           keyout6 : out  STD_LOGIC_VECTOR (15 downto 0));
22
end keygenerator;
23
24
architecture Behavioral of keygenerator is
25
26
  shared variable key0 : std_logic_vector (127 downto 0);
27
  shared variable key1 : std_logic_vector (127 downto 0);
28
  shared variable key2 : std_logic_vector (127 downto 0);
29
  shared variable key3 : std_logic_vector (127 downto 0);
30
  shared variable key4 : std_logic_vector (127 downto 0);
31
  shared variable key5 : std_logic_vector (127 downto 0);
32
  shared variable key6 : std_logic_vector (95 downto 0);
33
  
34
  signal output : std_logic_vector (95 downto 0);
35
36
  
37
begin
38
39
    
40
  process (round, key)
41
    
42
  begin
43
44
    key0 := key;
45
    key1 := key0(102 downto 0) & key0(127 downto 103);
46
    key2 := key1(102 downto 0) & key1(127 downto 103);
47
    key3 := key2(102 downto 0) & key2(127 downto 103);
48
    key4 := key3(102 downto 0) & key3(127 downto 103);
49
    key5 := key4(102 downto 0) & key4(127 downto 103);
50
    key6 := key5(102 downto 7); 
51
  
52
    case round is
53
      when "0000" => output <= key0(127 downto 32);
54
      when "0001" => output <= key0(31 downto 0) & key1(127 downto 64);
55
      when "0010" => output <= key1(63 downto 0) & key2(127 downto 96);
56
      when "0011" => output <= key2(95 downto 0);
57
      when "0100" => output <= key3(127 downto 32);
58
      when "0101" => output <= key3(31 downto 0) & key4(127 downto 64);
59
      when "0110" => output <= key4(63 downto 0) & key5(127 downto 96);
60
      when "0111" => output <= key5(95 downto 0);
61
      when "1000" => output <= key6;
62
      when others => output <= (others => 'X');
63
    end case;
64
    
65
  end process;
66
67
  keyout6 <= output(15 downto 0);
68
  keyout5 <= output(31 downto 16);
69
  keyout4 <= output(47 downto 32);
70
  keyout3 <= output(63 downto 48);
71
  keyout2 <= output(79 downto 64);
72
  keyout1 <= output(95 downto 80);
73
  
74
end Behavioral;

von Achim S. (Guest)


Rate this post
useful
not useful
ok, next problem: in your testbench you use the two values "1100" and 
"1001" for round. Both values run into the "others" clause of your case 
structure and force the output to X.

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.