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Forum: FPGA, VHDL & Verilog Modelsim simulation OK but FPGA implementation incorrect!!


Author: Omar (Guest)
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I am designing a divide by 4/ divide by 8 module. Modelsim simulation 
runs as expected. However upon programming with Altera I get a funky 
output on d_out but clk_out is running as expected.

I have attached the project file which includes everything.

Author: dude (Guest)
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I dont like to open .rar. maybe single files ok?

Author: Lothar Miller (lkmiller) (Moderator)
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Omar wrote:
> I am designing a divide by 4/ divide by 8 module.
That's a few lines of code. Why do you post them in a rar?

Author: Omar Rashad (ojay77)
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity decimator2 is
  port (clk, sync, d_in: IN std_logic; 
        clk_out, d_out: OUT std_logic);
end decimator2;

architecture FSM of decimator2 is
type state is (s0, s1, s2, s3, s4, s51, s61, s71, s81, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16);
signal c_state: state := s0;
signal temp: std_logic;

begin

d_out <= temp;

process (clk)
begin
if (clk = '1' and clk'event) then
  case c_state is
    when s0 => if (sync = '1') then
        c_state <= s1;
         else
        c_state <= s0;
         end if;
    when s1 => if (sync = '1') then
        c_state <= s2;
         else
        c_state <= s0;
         end if;
    when s2 => if (sync = '1') then
        c_state <= s3;
         else 
        c_state <= s0;
         end if;
    when s3 => if (sync = '1') then
        c_state <= s4;
         else
        c_state <= s0;
         end if;
    when s4 => if (sync = '1') then
        c_state <= s5;
         else
        c_state <= s51;
         end if;
    when s51 => if (sync = '1') then 
        c_state <= s1;
          else
        c_state <= s61;
          end if;
    when s61 => if (sync = '1') then
        c_state <= s1;
          else
        c_state <= s71;
          end if;
    when s71 => if (sync = '1') then
        c_state <= s1;
          else
        c_state <= s81;
          end if;
    when s81 => if (sync = '1') then
        c_state <= s1;
          else
        c_state <= s51;
          end if;
    when s5 => if (sync = '1') then
        c_state <= s6;
         else
        c_state <= s0;
         end if;
    when s6 => if (sync = '1') then
        c_state <= s7;
         else
        c_state <= s0;
         end if;
    when s7 => if (sync = '1') then
        c_state <= s8;
         else
        c_state <= s0;
         end if;
    when s8 => if (sync = '0') then
        c_state <= s9;
         else
        c_state <= s1;
         end if;
    when s9 => if (sync = '0') then
        c_state <= s10;
         else
        c_state <= s1;
         end if;
    when s10 => if (sync = '0') then
        c_state <= s11;
         else
        c_state <= s1;
         end if;
    when s11 => if (sync = '0') then
        c_state <= s12;
         else
        c_state <= s1;
         end if;
    when s12 => if (sync = '0') then
        c_state <= s13;
         else
        c_state <= s1;
         end if;
    when s13 => if (sync = '0') then
        c_state <= s14;
         else
        c_state <= s1;
         end if;
    when s14 => if (sync = '0') then
        c_state <= s15;
         else
        c_state <= s1;
         end if;
    when s15 => if (sync = '0') then
        c_state <= s16;
         else
        c_state <= s1;
         end if;
    when s16 => if (sync = '0') then
        c_state <= s9;
         else
        c_state <= s1;
         end if;
    when others => c_state <= s0;
  end case;
end if;
end process;

process (c_state)
begin
case c_state is
  when s0 => temp <= '0'; clk_out <= '0';
  when s1 => temp <= '0'; clk_out <= '0';
  when s2 => temp <= '0'; clk_out <= '0';
  when s3 => temp <= '0'; clk_out <= '0';
  when s4 => temp <= '0'; clk_out <= '0';
  when s51 => temp <= d_in; clk_out <= '0';
  when s61 => temp <= temp; clk_out <= '1';
  when s71 => temp <= temp; clk_out <= '1';
  when s81 => temp <= temp; clk_out <= '0';
  when s5 => temp <= '0'; clk_out <= '0';
  when s6 => temp <= '0'; clk_out <= '0';
  when s7 => temp <= '0'; clk_out <= '0';
  when s8 => temp <= '0'; clk_out <= '0';
  when s9 => temp <= d_in; clk_out <= '0';    --beginning of decimate by 8
  when s10 => temp <= temp; clk_out <= '0';
  when s11 => temp <= temp; clk_out <= '1';
  when s12 => temp <= temp; clk_out <= '1';
  when s13 => temp <= temp; clk_out <= '1';
  when s14 => temp <= temp; clk_out <= '1';
  when s15 => temp <= temp; clk_out <= '0';
  when s16 => temp <= temp; clk_out <= '0';
end case;
end process;
end FSM;

I added a .rar file because I wanted to present all the project files, 
not just the source code.

Author: Omar (Guest)
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Bump!

Author: Lothar Miller (lkmiller) (Moderator)
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Omar R. wrote:
> the source code.
What's the intention of that code? What should it do? And what does it 
do instead?

Omar R. wrote:
>   port (clk, sync, d_in: IN std_logic
You must read about asynchronous inputs and about synchronizing inputs.
To keep things short: never ever use a async input in a FSM.

Author: Omar Rashad (ojay77)
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The intention is for it to divide the input data and input clock (d_iun, 
clk) by 4 or by 8 based on the length of the sync signal (if it is 4 
cycles long then divide by 4, if 8 then divide by 8).

d_out should be basically a sampled and held d_in (held for 4 or 8 
cycles). Currently it is not being held correctly. However, clk_out is 
correct.

Author: daniel__m (Guest)
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Omar R. wrote:
> process (c_state)

rethink the sensitivity list of your second process. the simulation my 
be wrong.

Author: Lothar Miller (lkmiller) (Moderator)
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Indeed the synthesizer should report something about an incomplete 
sensitivity list...

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