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Forum: FPGA, VHDL & Verilog DDR2 connecting


Author: Jost (Guest)
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Hi!

I am designing a board with FPGA and DDR2 memory. I am using Lattice XP2 
chip with integrated blocks for interfacing DDR memory. However in 
datasheets I cannot find information about how addressing timings work 
and to which pins should address lines be connected. Fast I/O's are only 
for data lines.
Can somebody point me in the right direction here? Where can I get more 
information about this topic?

Regards, Jost

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