EmbDev.net

Forum: FPGA, VHDL & Verilog using expression in instatiation


von guest (Guest)


Rate this post
useful
not useful
Hi

I have 2 component instatiation

inst1 : test_component
        port map (
            b_in => in_sig,
            a_out => sig_x(7 downto 0)

        );
inst2 : component2
        port map (
            c => sig_x(3 downto 0)&sig_x(7 downto 4),
            d => out_sig
        );

for testing purpose, i have to swap the vectors in inst2 ( c => sig_x(3 
downto 0)&sig_x(7 downto 4))

i tried this ..

sigc<=sig_x(3 downto 0)&sig_x(7 downto 4);
inst2 : component2
        port map (
            c => sigc,
            d => out_sig
        );
it still does not work ...i read that expressions can be used in 
instantiation when the operands are contants ...is there any other way 
to solve this?

Please log in before posting. Registration is free and takes only a minute.
Existing account
Do you have a Google/GoogleMail account? No registration required!
Log in with Google account
No account? Register here.