Forum: FPGA, VHDL & Verilog using expression in instatiation

Author: guest (Guest)
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I have 2 component instatiation

inst1 : test_component
        port map (
            b_in => in_sig,
            a_out => sig_x(7 downto 0)

inst2 : component2
        port map (
            c => sig_x(3 downto 0)&sig_x(7 downto 4),
            d => out_sig

for testing purpose, i have to swap the vectors in inst2 ( c => sig_x(3 
downto 0)&sig_x(7 downto 4))

i tried this ..

sigc<=sig_x(3 downto 0)&sig_x(7 downto 4);
inst2 : component2
        port map (
            c => sigc,
            d => out_sig
it still does not work ...i read that expressions can be used in 
instantiation when the operands are contants ...is there any other way 
to solve this?


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