Hi everyone, just had 2 ideas and wanted to get some opinions on them.
I have a signal that I am wanting to debounce by code vs discrete 
components. Ive been running an example code that generates a interrupt, 
then counts up to a set number of bits, then samples the signal and 
outputs what it sampled, this is good for a basic push button, but I 
have a very timing critical application that will need some 
experimenting with and therefor having this done in code would be 
faster. My plan is to create a type of capacitor in vhdl, a simple count 
up by "x" when high, and count down by "y" when low, this will allow me 
to create "full" and "empty" thresholds on the fly and hopefully less 
glitches or late signal changes than desired.

The second version would check to see if the prior state was held to 
certain amount of time to decide if there was a glitch or intended state 
change. the signal sampled will have a high time varying between 1.5ms 
to 5ms and the low between 4ms to 200ms. Here's a quick example. Let me 
know what you think please.

 counter_set <= flipflops(0) xor flipflops(1);
 -- single clk wide pulse interrupt whenever signal changes states.

  PROCESS(clk)
  BEGIN
    IF rising_edge(clk) THEN
      flipflops(0) <= SIGNAL;
      flipflops(1) <= flipflops(0);

      If(counter_set = '1') THEN
       if offtime > 50000 and ontime <2500  then
        if flipflops(1) = '1' then
            SIGNAL_OUT <= 1;
            ontime <= 0;
            offtime <= 0;

      ELSIF ontime > 50000 and offtime <2500 THEN
         if flipflops(1) = '0' then
            SIGNAL_OUT <= 0;
            offtime <= 0;
            ontime <= 0;
      ELSE
       null;
             END IF; END IF ;END IF; END IF; END IF;

           if flipflops(1) = '1' then
              ontime <= ontime + 1;
               else
                offtime <= offtime + '1';
                  end if;

      END IF; END PROCESS;