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Forum: FPGA, VHDL & Verilog How to create our own IP core in Xilinx ?


Author: Sarang SSS (Company: Sasken) (sarang5s5s)
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I have designed a synthesizable verilog code. I want to create it's IP 
core and use it whenever I required in other modules or designs. Can 
someone please help me how to create our own IP core in Xilinx ?

Author: Klakx (Guest)
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ug1119 of Xilinx is a very good start

Author: Sarang SSS (Company: Sasken) (sarang5s5s)
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Thanks... :-)

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