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Forum: FPGA, VHDL & Verilog bad synchronous description - ISE synthesis error


Author: Farzam (Guest)
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Hello everybody. I have written the following VHDL code in ISE. In the 
synthesis report I am having this error saying:

"line 100: Signal wea_sig cannot be synthesized, bad synchronous 
description. The description style you are using to describe a 
synchronous element (register, memory, etc.) is not supported in the 
current software release."

I can't find the problem. I would be really thankful if someone could 
help me here.

here is my code:



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity main_code is
    Port ( clk : in  STD_LOGIC;
          edone: out std_logic := '0'
        );
end main_code;



architecture Behavioral of main_code is


signal dout_rom: STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => '0');
signal address_rom: std_logic_vector(3 downto 0) :=(others => '0');
------------- component rom
COMPONENT rom_core
  PORT (
    clka : IN STD_LOGIC ;
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
    );
END COMPONENT;
-------------

signal wea_sig: STD_LOGIC_VECTOR(0 DOWNTO 0) :="0" ;
signal address_ram: std_logic_vector(3 downto 0) :=(others => '0');
signal din_ram: STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => '0');
signal dout_ram: STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => '0');
------------- component ram
COMPONENT ram
  PORT (
    clka : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
  );
END COMPONENT;
-------------

signal counter: integer := 0;
signal counter_prime: integer := 0;
signal ero: std_logic_vector(7 Downto 0):=(others => '1');

begin

------port map rom
pm1 : rom_core
  PORT MAP (
    clka => clk,
    addra => address_rom,
    douta => dout_rom
  );
---

------port map ram
pm2 : ram
  PORT MAP (
    clka => clk,
    wea => wea_sig,
    addra => address_ram,
    dina => din_ram,
    douta => dout_ram
  );
---


(line 100)  process(clk)
begin

    if (counter_prime <9) then

          if(clk'event and clk='1') then
            counter <= counter + 1;
          wea_sig <= "0";
          din_ram <= ero;
       end if;



       if(clk'event and clk='0') then


           if(dout_rom < ero and counter/= 5)  then
                     ero <= dout_rom;
                end if;


           if(counter=1 or counter=3) then
               address_rom <= address_rom + 1;
           end if;


             if(counter=2) then
                address_rom <= address_rom + 3;
           end if;


           if(counter=4) then
              for i in 1 to 2 loop
                 if (counter_prime = i*3) then
                    address_ram <= address_ram + 2;
                        else
                            if(counter_prime /= 0 and i=1) then
                                address_ram <= address_ram + 1;
                    end if;
                        end if;
              end loop;
                    for i in 1 to 2 loop
                  if (counter_prime = (3*i)-1) then
                    address_rom <= address_rom - 3;
                else
                    if (i=1) then
                       address_rom <= address_rom - 4;
                   end if;
                end if;
                    end loop;
            end if;


           if(counter=5) then
               wea_sig <= "1";
              counter_prime <= counter_prime + 1;  --end of each round

              --getting ready for the next round
                    counter <= 0;
              ero <= (others => '1');
           end if;

       end if;

    end if;

    if(counter_prime=9) then
      edone <= '1'; --erosion is done
    end if;

end process;

end Behavioral;

Author: Lothar Miller (lkmiller) (Moderator)
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Farzam wrote:
> if (counter_prime <9) then                             if(clk'event and
> clk='1') then
Where did you find this very special way to describe a counter?
What does the manual of your synthesizer say to that?
A synchronous design usually starts with
if rising_edge(clk) then...

The design looks lousy due to the use of both clock edges. If I were 
your teacher I would give it back for rework until only one and the same 
clock edge is used throughout the whole design.

Author: Farzam (Guest)
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Thank you for the help. Actually I am new to synthesis and this code was 
only supposed to simulate the algorithm at the first place which did 
fine. It seems that I have to do more studies on synthesis.

If it is not a problem I would ask another question. Now I am trying to 
write the datas from the ram to a text file. I have added the process 
bellow to my code:


process(clk)

    file outfile: chartype;
    variable c: std_logic_vector(7 DOWNTO 0);

begin

    if(clk'event and clk='1' and counter_prime = 10) then
       counter <= counter + 1;
   end if;

    if(clk'event and clk='0' and counter_prime = 10 and counter < 16) 
then
       file_open(outfile,"C:\write.txt",write_mode);
      c:= dout_ram;
      write(outfile, tochar(c));
   end if;

end process;


in which 'tochar' is a function that converts std_logic_vector(7 downto 
0) s (outputs of the ram) to character. tochar is defined as bellow:

------- tochar function
function tochar (vec: std_logic_vector (7 DOWNTO 0)) return character is
variable ch: character;
begin
    case vec is
       when "00000000" => ch:= '0';
      when others => ch:= '1';
   end case;
return ch;
end tochar;
-------

The check syntax of the code is ok, but no .txt file is produced. I 
would be pleased if you could help.

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