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Forum: FPGA, VHDL & Verilog Speed up Modelsim Simulation


Author: Andy (Guest)
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How Can I get modelsim to run faster for simulation rather than 
something in the Pico second range (time interval)? Are there any other 
methods for speeding up simulation? It takes 45 minuts to get to 1ms as 
of now. I want the simulation to run for 20 ms to check on certain 
counters, timer modules and events. The System Clock runs on 50MHz.

And if there is an option will there be any drawbacks. For example 
missing events etc.?

Thanks

Author: Lothar Miller (lkmiller) (Moderator)
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Andy wrote:
> How Can I get modelsim to run faster
What version of ModelSim do you use?

Author: Andy (Guest)
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ModelSim ALTERA STARTER EDITION 10.4b

Author: Lothar Miller (lkmiller) (Moderator)
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Andy wrote:
> STARTER EDITION
Found a part of the problem...

And now of interest: how much lines of code has your design?

https://www.altera.com/products/design-software/mo...

Author: Andy (Guest)
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Yes. That could be a problem.

Around 5000 lines as an entire system.

I did try simulating as a separate module which is comparatively faster. 
But there are events which are triggered during the period which needs 
to be tested. This depends on the other modules in the system.

Author: VHDL hotline (Guest)
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Would be interesting how Mentor counts the lines. It may be possible to 
write a script that just replaces the \n\r by whitespaces in source 
code.

For my (unlimited) ModelSim version, sim works significantly slower when 
logging all signals to the wlf file vs. logging only the relevant 
signals. Also, when the wlf file is on network storage, this decreases 
sim speed.

Also check the vsim -t option, it determines the resolution of sim (but 
I don't know if it is speed relevant).

Author: Andy (Guest)
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> Also check the vsim -t option, it determines the resolution of sim (but
> I don't know if it is speed relevant).

But do you have any idea by using vsim -t 10ns would not ignore any 
events or skip counts during the simulation?

Author: VHDL hotline (Guest)
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Of course you should use a timing resolution that is suitable for your 
design. I use -t 1ps for "usual" (50-250 MHz) FPGA designs. You could 
only check if, by accident, it is set to e.g. fs which may decrease your 
sim speed.

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