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Forum: FPGA, VHDL & Verilog VHDL: Port map with std_logic_vector


Author: LiZhen L. (Guest)
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I'm trying to simulate a ring oscillator driving a 6-bit counter. The 
counter works fine. I've declared a new signal to store the output from 
the counter, but I'm not so sure about the port map for the counter when 
I included it as a part of the ring oscillator.
--6 BIT COUNTER (works fine)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.All;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY counter_vhdl IS
PORT (clock,reset     : IN std_logic;
      output          : OUT std_logic_vector(0 TO 5));
END counter_vhdl;

ARCHITECTURE behav OF counter_vhdl IS 
CONSTANT Tdelay  : time := 10 ns; -- Typical delay

BEGIN

check_clock : PROCESS(clock, reset)
VARIABLE count  : std_logic_vector(0 TO 5) := "000000";
BEGIN
            
IF ( reset = '0') THEN
  count := "000000";
  ELSIF ( clock'event and clock = '1') THEN
    IF (count = "111111") THEN
      count := "000000";
    ELSE
      count :=  count + "000001";
    END IF;
END IF;
  output <= count AFTER Tdelay;

END PROCESS check_clock;
END behav;


--Ring oscillator with counter

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.All;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY ring_vhdl IS
PORT(  ring_osc_enb,reset   : IN std_logic;
       OUT1, OUT2    : OUT std_logic; 
       data_out      : OUT std_logic_vector(0 TO 5));
END ring_vhdl;

ARCHITECTURE struct OF ring_vhdl IS
  COMPONENT OSCILLATOR
    PORT (ENB: IN std_logic; OUT1, OUT2 : OUT std_logic);
  END COMPONENT;
  
  COMPONENT COUNTER 
               PORT(clock,reset: IN std_logic;
                    data_out   : OUT std_logic_vector(0 TO 5));
        END COMPONENT;

  signal osc1, osc2  : std_logic;
  signal count6     : std_logic_vector(0 TO 5);  

  FOR u1: OSCILLATOR USE ENTITY WORK.ring_oscillator_vhdl(struct);
  FOR u2: COUNTER USE ENTITY WORK.counter_vhdl(behav);
  
  BEGIN

    u1:OSCILLATOR PORT MAP(ring_osc_enb,osc1,osc2);
    u2:COUNTER PORT MAP(osc1,reset,count6);    <-----
    
    OUT1 <= osc1;
    OUT2 <= osc2;
    data_out <= count6;

END struct;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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And what's the problem now?

LiZhen L. wrote:
> but I'm not so sure about the port map for the counter
Indeed: an ascending bit order is unusual for counters. In your counter 
bit 5 is the fastest toggling bit. In 99.9999% around the world always 
bit 0 is the lowest and fastest toggling bit.
In short words: I would declare a vector always with "downto". Billions 
of people expect it that way...

For the port map: do not use positional assignment. Better use explicit 
assignment:
   u2:COUNTER PORT MAP(clock=>osc1,reset=>reset,data_out=>count6);

BTW: did you find that about the [vhdl] formatting options tags?

: Edited by Moderator

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