EmbDev.net

Forum: FPGA, VHDL & Verilog 3 bit output


Author: Ashuuu (Guest)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Hello,

I need to design 3 bit output, which are 000, 001, 010, 011, 100 using 
FPGA. I have already designed it. But, the problem is I can't get that 
desired output I want. I got 000, 001, 011 and 111 outputs. Here I 
attach my code and testbench and also Isim simulator waveform part.

Thank you.

Author: derLars (Guest)
Posted on:

Rate this post
0 useful
not useful
Hi Ashuuu,

first: the sensitivity list in your module "selectsig" is wrong. The 
whole process is only related to the clock. So only the clock should be 
in the list.

Second: in your testbench. First you assert s0, then you assert s1 -> 
what happens with s0 in that case?

Best regards,
derLars

Author: Ashuuu (Guest)
Posted on:

Rate this post
0 useful
not useful
Hi derLars,

Do you mean s0, s1, and s0 are output, not the input?

Author: Chris (Guest)
Posted on:

Rate this post
0 useful
not useful
You got what you designed.
In your testbench you set s0, s1, s2 to:
0,0,0 then
0,0,1 then
0,1,1 then
1,1,1

Which gives as result in your statemachine:
000
100
110
Don' care.

If you want different outputs you have to set them.

PS, it seems that  you get the desired output by just concatenate the 
input bits in the right oder.

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.