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Forum: FPGA, VHDL & Verilog Error in shift operator


von Hayder A. (Company: NA) (hayder)


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Hello:

I have this error in my verilog  code:
1
 case (aexp[14] ^ bexp [14])
2
     
3
        1'b0 :   bman = bman << (aexp- bexp);
4
        1'b1 :   bman = bman << (aexp+ bexp);
5
        
6
       endcase

here, if the sign bit [14] is equal, so sub aexp - bexp then shift the 
bman by the difference.
or if they are not equal so add them and shift.

but in my simulator I cant see bman shift at all, so i change the code 
to :
1
 case (aexp[14] ^ bexp [14])
2
     
3
        1'b0 :   diff = bman << 3;//(aexp- bexp);
4
        1'b1 :   diff = bman << 2;//(aexp+ bexp);
5
        
6
       endcase

also there is no value in diff !!
could you please help me
thanks

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