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Forum: FPGA, VHDL & Verilog query related to verilog code


Author: Thahseen (Guest)
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module encoder(clk,rst,en,en1,data,decoded_data);
    input clk,rst,en,en1;
    input [7:0]data;
    output [7:0]decoded_data;
    wire [7:0]btg;
    reg [7:0]dec;
    reg [5:0] mem[0:255];   // ENCODED
    reg [5:0] mem1[0:255];  // DECODED
    reg [7:0] mem2[0:255];  // OUTPUT
    reg [7:0] mem3[0:255];  // BTG DATAS
    reg [7:0]count,count1,count2;
    integer fd;
  
 always @(!rst) begin
        mem[0]=6'b000000;  
        mem1[0]=6'b000000;
        mem2[0]=8'b00000000;
        mem3[0]=8'b00000000;
        count=8'b00000000;
        count1=8'b00000000;
        count2=8'b00000000;
        dec=8'b00000000;
    end
    
    
    
    //pseudo_random p1(clk,rst,data);
    binary_gray b1(data,btg);
    
    
    
    always @(data) begin
        fd=$fopen("outfile.txt");
        $fdisplay(fd,"%b",data);
    end
        
    
    
    always @(btg) begin
        if (btg[4] && btg[5] && en == 1) begin
            count=count+1;
            mem3[count]=btg;
            mem[count]=~({btg[7],btg[6],btg[3],btg[2],btg[1],btg[0]} ^ mem[count-1]);
            fd=$fopen("outfile1.txt");
            $fdisplay(fd,"%b",mem[count]);
        end else if (en == 1) begin
            count=count+1;
            mem3[count]=btg;
            mem[count]=({btg[7],btg[6],btg[3],btg[2],btg[1],btg[0]} ^ mem[count-1]);
            fd=$fopen("outfile1.txt");
            $fdisplay(fd,"%b",mem[count]);
        end
    end
    
    always @(btg) begin
        if ((btg[4] && btg[5]) && en1 == 0) begin
            count1=count1+1;
            mem1[count1]=~((mem[count-1]) ^ (mem[count]));
            dec={mem1[count1][5],mem1[count1][4],btg[5],btg[4],mem1[count1][3],mem1[count1][2],mem1[count1][1],mem1[count1][0]};
            fd=$fopen("outfile2.txt");
            $fdisplay(fd,"%b",mem1[count1]);
        end else if (en1 == 0) begin
            count1=count1+1;
            mem1[count1]=((mem[count-1]) ^ (mem[count]));
            dec={mem1[count1][5],mem1[count1][4],btg[5],btg[4],mem1[count1][3],mem1[count1][2],mem1[count1][1],mem1[count1][0]};
            fd=$fopen("outfile2.txt");
            $fdisplay(fd,"%b",mem1[count1]);
        end
    end
    
    
    gray_binary g1(dec,decoded_data);
    
    
    always @(btg) begin
        count2=count2+1;
        mem2[count2]=decoded_data;
        fd=$fopen("outfile3.txt");
        $fdisplay(fd,"%b",mem2[count2]);
    end
        
endmodule

module binary_gray(a,b);
    input [7:0]a;
    output [7:0]b;
    wire [7:0]b;
    assign b={a[7],a[7]^a[6],a[6]^a[5],a[5]^a[4],a[4]^a[3],a[3]^a[2],a[2]^a[1],a[1]^a[0]};
endmodule

module gray_binary(a,b);
    input [7:0]a;
    output [7:0]b;
    wire [7:0]b;
    assign b={a[7],a[7]^a[6],b[6]^a[5],b[5]^a[4],b[4]^a[3],b[3]^a[2],b[2]^a[1],b[1]^a[0]};
endmodule


module pseudo_random(clk,rst,s);
input clk,rst;
output [8:1]s;
reg [8:1]s;
wire s0;
// MODULO 2 ADDITION
assign s0 = s[2] ^ s[3] ^ s[4] ^ s[8];
// STATE MACHINE
always @ (posedge clk or rst) begin
// INITIAL STATE SHOULDN'T BE 000 => 100
if(!rst) begin
s[1] <= 0;
s[2] <= 0;
s[3] <= 0;
s[4] <= 0;
s[5] <= 0;
s[6] <= 0;
s[7] <= 0;
s[8] <= 1;
end else begin
s[1] <= s[2];
s[2] <= s[3];
s[3] <= s[4];
s[4] <= s[5];
s[5] <= s[6];
s[6] <= s[7];
s[7] <= s[8];
s[8] <= s0;
end
end
endmodule


line 15: Unexpected event in always block sensitivity list.

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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I don't know Verilog too much, but counters without a clock form 
combinatorial loops:
    ...
    always @(btg) begin
        if (btg[4] && btg[5] && en == 1) begin
            count=count+1;
    ...
    always @(btg) begin
        count2=count2+1;
    ...
And so forth.
Additionally to me it looks like some of those lists are incomplete:
In the qouted blocks above count and count2 are missing.

For the error message:
Try your code without the '!'.
A sensitivity list tells only to look for changes on the signals in 
it. So a negation sign is absolutely useless there. Think about that...


BTW: pls use [pre], [code] or [c] tags around your code.

: Edited by Moderator
Author: Lattice User (Guest)
Posted on:

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>
> For the error message:
> Try your code without the '!'.
> A sensitivity list tells only to look for changes on the signals in
> it. So a negation sign is absolutely useless there. Think about that...
>
Verilog allows expressions in the sensitivity list, but as with many 
constructs the synthesizer does not. However Lothar is right the ! does 
not do anything, a negated change is still a change.

Another problem with the code, is that the synthesizer does not allow 
assignments to a signal from multiple always blocks. Also legal in 
Verilog but not part of synthesizable subset.

I strongly suggest reading the coding style guide of the tool chain!

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