Forum: FPGA, VHDL & Verilog Use Xilinx Microblaze performance monitoring engine from AXI4Lite

Author: Giacomo Valente (giav)
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I would like to use the MicroBlaze performance monitoring engine to 
collect some information on my application code running on the processor 
itself. I would need these information at application level. I have a 
problem to access these values.

In order to do these things, I have created a project with MicroBlaze 
and extended debug function, with 5 event counters and 1 latency 

Then I have inserted a MDM in my design and created an AXI4lite slave 
port to access from MicroBlaze itself. In this mode I should be able to 
access to internal performance monitoring engine by using DBG_CTRL and 
DBG_DATA registers indicated to page 12 of pg115 (MDM product guide), 
with values indicated on page 92 of MB reference guide (version 

Suppose I need to measure number of any valid executed instruction, I 
have wrote the code attached to this post.

The problem happens when I perform the read from *dbg_data: the read 
action on this variable does not give any response.

The register pointed by variable is R/W.

Do you have any suggestion about this wrong behaviour?

Thank you.

Author: Duke Scarring (Guest)
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Try to define your *dbg_data as volatile.


Author: Giacomo Valente (giav)
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thank you for the suggestion. I have tried and the behaviour is the 
The problem is the AXI engine under the AXI4slave peripheral (in this 
case, the microblaze debug module): it does not answer to a request.
In the previous post, I have indicated that the problem is the read 
action from *dbg_data. By making a simulation, it appears that the 
problem also happens during an AXI write on *dbg_data memory area.
More specifically, considering attached file, and focusing on MDM 
section, it can be noted that a write on address 41400010 (the content 
of dbg_ctrl variable) happens correctly, because there is a READY 
response from slave to a VALID transition.
Then, there is a write on address 41400014 (the content of dbg_data 
variable): there is no READY response.
The above first two writes are related to the first lines of the code:

This causes a block in the application execution, because following AXI 
guidelines, if a master issues a request to write and raises up the 
VALID signal, it must wait the READY response from slave. So without 
READY answering, the master is blocked.

Do you have other suggestion?

Thank you,


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