Forum: FPGA, VHDL & Verilog Blocking vs Non-blocking questions (verilog)

Author: Trevor Hill (Company: Raytheon) (trevh88)
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1. I can't remember learning this specifically but for some reason I 
think you are not supposed to use blocking in sequential blocks? If so 
why is this?

2. I was taught that if blocking is used, but would still be 
functionally the same as non blocking, it synthesizes the same as non 
blocking, i.e a single = statement within an always block. I answered 
this way in an interview once and was told I was wrong, that they do 
synthesize differently. So, which is it? How does synthesis handle 
blocking vs non-blocking?

: Edited by User
Author: Marcus Harnisch (mharnisch)
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Trevor H. wrote:
> 1.

This rule applies to variables driven and read by different processes.

The core of the issue is in Verilog's scheduling semantics (cf. 
IEEE1800-2012, sec. 4.4 “Stratified event scheduler”). Blocking 
assignments take place in the Active region, that is as soon as the 
corresponding statements are executed. Non-blocking assignments will be 
scheduled into the NBA region, that is after all statements have 

IOW, the non-blocking assignment ensures that all processes that are 
looking at a variable will see the value it had before any changes in 
the current time step. Much like a VHDL signal (but not quite the same).

> 2.

As far as a single assignment statement is concerned, I'd say this is 
true. But if there is an assignment before reading back the variable, 
blocking vs non-blocking does synthesize differently.

¹ Simplified. There are loopholes. Verilog gives you enough rope to hang 


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