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Forum: FPGA, VHDL & Verilog Flashing digits from 0 to 9


Author: Ber 25 (ber25)
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Hi , Can you help me to write the vhdl file for next delivery?

Design and implement a circuit that successively flashes digits from 0 
to 9 on the 7-segment display HEX0. Each digit should be displayed for 
about one second. Use a counter to determine the one-second interval. 
The counter should be incremented by the 50 MHz clock signal provided on 
the DE2 board (CLOCK_50 input signal, to be managed as a clock input 
coming from the external world). Do not derive any other clock signals 
in your design; make sure that all the flipflops in your circuit are 
clocked directly by the 50 MHz clock signal.

Author: Lothar Miller (lkmiller) (Moderator)
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Ber 2. wrote:
> Can you help me to write the vhdl file for next delivery?
Show what you have, then maybe one will help you.
But I don't think anyone is going to do your homework completely...

Author: Ber 25 (ber25)
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Lothar M. wrote:
> Ber 2. wrote:
>> Can you help me to write the vhdl file for next delivery?
> Show what you have, then maybe one will help you.
> But I don't think anyone is going to do your homework completely...
library ieee;
use ieee.std_logic_1164.all;

entity flashing_LIGHTS is
port (  CLOCK_50, KEY0 : in std_logic;
    HEX0 : out std_logic_vector(0 to 6));
end flashing_LIGHTS;

architecture semi_behavioral of flashing_LIGHTS is

component counter_4bit is
port(  
               enable,clk,clear:in std_logic;
    Q: buffer std_logic_vector(3 downto 0));
end component;

component segment_7_decoder is
PORT (a :IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
      B :OUT STD_LOGIC_VECTOR(0 TO 6));
end component;

signal count_enable, clock, reset : std_logic;
signal count : std_logic_vector(3 downto 0);

begin

clock<=CLOCK_50;
reset <= KEY0;

clock_counter: process (clock, reset)
variable count : integer range 0 to 49999999;
begin
if reset = '1' then
count := 0;
count_enable<='0';
elsif clock'event and clock='1' then
  if count = 49999999 then
  count_enable<='1';
  count:=0;
  else
  count := count+1;
  count_enable<='0';
  end if;
end if;
end process;

counter: counter_4bit port map
(count_enable, clock, reset or (count(3) and count(0)), count);

RAPP: segment_7_decoder port map(count, HEX0);
end semi_behavioral;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
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Lothar M. wrote:
> Show what you have
Why not implementing the 4 bit counter simplay as a counter from 0 to 9 
in the flashing_LIGHTS entity?
library ieee;
use ieee.std_logic_1164.all;

entity flashing_LIGHTS is
port (  CLOCK_50, KEY0 : in std_logic;
        HEX0 : out std_logic_vector(0 to 6));
end flashing_LIGHTS;

architecture semi_behavioral of flashing_LIGHTS is

signal count : integer range 0 to 9 := 0;
signal countsec : integer range 0 to 49999999 := 0;

begin

clock<=CLOCK_50;
reset <= KEY0;

clock_counter: process (CLOCK_50, reset)
begin
if reset = '1' then
  count_enable<='0';
elsif clock'event and clock='1' then
  if countsec = 49999999 then -- one second is gone
    countsec <= 0;
    if count<9 then -- each second: increment the digit counter
      count <= count+1;
    else
      count <= 0;
    end if;
  else
    countsec <= count+1;
  end if;
end if;
end process;

HEX0 <= "1111110" when count=0  else
        "0110000" when count=1  else
        ...
        "1111111" when count=8  else
        "1110011"; --  count=9

end semi_behavioral;
If you must use those 2 components counter_4bit and segment_7_decoder, 
then you will have to rip out the corresponding lines of code and put 
them in their own entities...


BTW:
Have a look at the few lines above the reply edit box:
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So pls attach VHDL code as *.vhdl file or use the [vhdl] tokens further 
on.

: Edited by Moderator

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