EmbDev.net

Forum: FPGA, VHDL & Verilog upcounter with enable signal for one clock cycle


Author: felix89 (Guest)
Posted on:

Rate this post
0 useful
not useful
______|``|________________________|``|_______       ---->enable input
________________________________________________
_______<0><1><2><3><4><5><5><5><5><0><1><2><3><4>  ---->counter output

hello leute,

i need your suggestions. i need to design a synthesizable up counter 
which starts counting if it finds enable signal toggling from one to 
zero..and  once count limit is reached, it has to wait for next enable 
pulse to start the next counting cycle again.

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
felix89 wrote:
> i need your suggestions. i need to design a synthesizable up counter
> which starts counting if it finds enable signal toggling from one to
> zero..
What language?
What target?
Whats the counting clock?
Whats the system clock?


BTW: do you know the German forum?
https://www.mikrocontroller.net/forum/fpga-vhdl-cpld
Maybe you want to switch over ther?

Author: felix89 (Guest)
Posted on:

Rate this post
0 useful
not useful
vhdl,starix,same clock

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Thats it:
:
signal olden : std_logic := '0';
signal cnt   : integer range 0 to 99 := 0;
:
:
process begin
   wait until rising_edge(clk);
   if (olden='0' and en='1') then -- "rising edge" of enable input
      cnt <= 0;
   elsif (cnt<99)                 -- saturate counter at 99
      cnt <= cnt+1;
   end if;
   olden <= en;                   -- remember "last" enable value
end process;

If the enable input is a async signal one flipflop stage (at least) 
must be added for syncing to the system clock:
:
signal ensr  : std_logic_vector (1 downto 0) := "00";
signal cnt   : integer range 0 to 99 := 0;
:
:
process begin
   wait until rising_edge(clk);
   if (ensr="01") then   -- "rising edge" of enable input
      cnt <= 0;
   elsif (cnt<99)        -- saturate counter at 99
      cnt <= cnt+1;
   end if;
   ensr <= ensr(0) & en; -- shift register for syncing and edge detection
end process;

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
If the enable is synchronous and active for only one clock cycle, then 
it is extremely simple:
:
signal cnt   : integer range 0 to 99 := 0;
:
:
process begin
   wait until rising_edge(clk);
   if (en='1') then -- restart on enable signal
      cnt <= 0;
   elsif (cnt<99)                 -- saturate counter at 99
      cnt <= cnt+1;
   end if;
end process;

: Edited by Moderator
Author: Chris (Guest)
Posted on:

Rate this post
0 useful
not useful
Even if this is just a finger exercise, mostly it doesn't (really) help 
people if you do their homework.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Chris wrote:
> it doesn't (really) help people if you do their homework.
I could have written half a book, but I think, felix89 learns more by 
comparing those 3 solutions...

And additionally felix89 will ask himself (or he max be asked by his 
teacher) why the "wait until" is used here. And to find that answer will 
be a nice learning process too...

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.