Forum: FPGA, VHDL & Verilog FPGA Frequency Divider

Author: _Jaiko 007 (jaiko)
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I need to design frequency divider that adjusts the clock frequency from 
50MHz to 200Hz so that it generates 200 pulse signal every second by 
using FPGA. I'm using Xilinx and the language that I used is VHDL 
language. I got stuck because I can't get the output. The frequency 
divider has 2 input ports and 1 output port. Here I attach my code.


Author: Mr. FPGA (Guest)
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dude, there so many frequency devider threads in this and other Forums, 
that the solution is just a Google click away.

regarding your code: it should be advisable to discuss this with your 
teachers to figure out your false appraoch to this subject

golden way: design with real components and learn vhdl after having the 
knowledge how circuits do operate

Author: Lothar Miller (lkmiller) (Moderator)
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Mr. FPGA wrote:
> false appraoch to this subject
Indeed one MUST NOT generate a derived clock out of the one and only 
FPGA clock by using a counter. The only practical way is to create a 

So throughout the whole design there's only 1 clock and every other job 
is done by enable signals that are generated out of that clock being 
valid for 1 clock cycle.

See the creation of a 3 Hz clock enable for a chasing light there:
There you can see: only 1 clock is used throughout the whole design...

And: use integers for counters. That makes the code easily readable even 
for humans...

: Edited by Moderator


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