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Forum: FPGA, VHDL & Verilog Vhdl file reading: reading integer(varying length) and converting to std_logic_vector


Author: felix89 (Guest)
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Hello all,

I have to read a file for a vhdl test bench.
the text file has integers in the range of 1 digit to 4 digits.

which textio function should i use for reading integer of varying length 
and covert this integer  to std_logic vector?.

eg:-
0
0
1
5
6
3
76
23
97
12
132
174
3452
4056

Author: Duke Scarring (Guest)
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