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Forum: FPGA, VHDL & Verilog Frequency Divider using VHDL


Author: _Jaiko 007 (jaiko)
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Hello,

I need to do a code for frequency divider from 20MHz to 10kHz of PWM 
using Xilinx. I want to know how doing it. I try my best to do the code, 
but I still can't get the output. So, I need your help because I'm still 
new with FPGA.

Thanks.

Author: Lothar Miller (lkmiller) (Moderator)
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Syu H. wrote:
> I try my best to do the code, but I still can't get the output.
Show what you have and what you tried. And say what you expected and 
waht you get istead. Then someone can help you.

I could simply give you a link to such a code, but then YOU won't learn 
nothing at all. Got the point?


> I need to do a code for frequency divider from 20MHz to 10kHz
BTW: you MUST NOT generate a 10kHz "clock" to be used inside a FPGA as a 
real clock. A beginners design has exactly 1 clock in whole. All the 
rest is done by clock enables!

Author: Dima Ustinoff (ustinoff)
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A simple way to create a clock divider is a counter.

How we can implement a counter in VHDL?
signal count : std_logic_vector (data_width-1 downto 0) := (others=>'0');

process(clk)
begin
if rising_edge(clk) then
if unsigned(count) = YOUR_COUNT_VALUE then
count <= (others=>'0');
else
count <= std_logic_vector (unsigned(count)+1);
end if;
end if;
end process; 

You need to add one more signal in this code and you will get your 
divider.

Author: Lothar Miller (lkmiller) (Moderator)
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Dima U. wrote:
> How we can implement a counter in VHDL?
You are in a very, very lucky condition: you are not the first on world 
to solve that problem.

> You need to add one more signal in this code and you will get your
> divider.
I don't think the target of this simple exercise is to ask in a forum. 
Instead YOU should (at least) try to solve that homework on your OWN.

And thats the way we gonna do it: YOU try it and when you have a 
specific problem, dne you tell what YOU tried, what you expected, why 
you expected it and what you got instead.

Be sure it would have cost me less time to solve your exercise than to 
write this short manual for your homework. But maybe its worth the 
time...

: Edited by Moderator
Author: Dima Ustinoff (ustinoff)
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Lothar M. wrote:
> Dima U. wrote:
>> How we can implement a counter in VHDL?
> You are in a very, very lucky condition: you are not the first on world
> to solve that problem.
>
>> You need to add one more signal in this code and you will get your
>> divider.
> I don't think the target of this simple exercise is to ask in a forum.
> Instead YOU should (at least) try to solve that homework on your OWN.
>
> And thats the way we gonna do it: YOU try it and when you have a
> specific problem, dne you tell what YOU tried, what you expected, why
> you expected it and what you got instead.
>
> Be sure it would have cost me less time to solve your exercise than to
> write this short manual for your homework. But maybe its worth the
> time...


I understand. I did not write the final version of divider. The counter 
is only first step.

: Edited by User
Author: Lothar Miller (lkmiller) (Moderator)
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Dima U. wrote:
> The counter is only first step.
Always the first step is the biggest in mankind. Do it.

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