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Forum: FPGA, VHDL & Verilog LUT in verilog


Author: Antonio Angelino (lsdv)
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Hi guys, I have a problem with
creation of a lookup table in verilog. I want
to export data from matlab to a verilog file. It
is a lut with one input and one output. Can you suggest
me a command for avoiding write about 200 line of code.


Thanks.

Author: Andi Meerbann (Guest)
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you could write a Matlab script printing the relevant code snippet 
(inside of a case block) in verilog syntax. Something like this 
(untested!) Matlab code here:

for i=1:length
 fprintf('8'h%x: out <= 8'h%x\n', i, value(i));
end

The result you copy & paste into you verilog file.

Author: Antonio Angelino (lsdv)
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Ok, this is a good way to solve problem of copy,Thanks.
But about the LUT creation itself?

For example if i want a LUT of a function sqrt((1/x)+1) with input fixed 
because i have a fixed point representation, how can i get the function 
output?

Is there a function ?


excuse me, but i've never done this.

Author: Andi Meerbann (Guest)
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Of course there is a function in Matlab to calculate this. And there is 
the function fixdt() in Matlab to create a fixed point representation of 
your numbers.

This is more a Matlab problem rather than a Verilog problem, right?

Author: Antonio Angelino (lsdv)
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well, I ned info about connection of the 2 softwares... you gave me.
Finally I was able to create this lut.
Now I can continue to study Verilog.

Thank you, Mr Meerbann.

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