Forum: FPGA, VHDL & Verilog Problems in constraining Negative setup slack

Author: Glen (Guest)
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Hello all,

I am facing problems in constraining Negative Slacks (for a 50Mhz clock 
and 150MhZ clock both generated clocks). I had a negative slack of -59 
which was because of using a 44_24 LPM divider which I solved using 2 
stages of pipeline. There were few other slack issues which I 
constrained using set_clock_groups and a set_false_path.

Now, I have setup negative slack of -14 and -6 (two different generated 
clocks) within a module where the input to the module comes from a 
written register(in SW), using which a division is performed and the 
value is stored in a register. The same happens with one more module. I 
am not sure why lot of timing issues come up with Division (Be it using 
lpm or a simple arithemtic division).

I am not very familiar with timing analysis, and I am not sure if I 
should alter the code which can solve the timing issues or use 
constraints set_false_path  multicycle paths  setting max delays to 
ignore the constraints. I dont want to alter the code much which has 
been already tested.

I am attaching the Setup Timing Closure Report, the Source code of the 
module and the SDC File.(see attachments)

Looking forward to your suggestions! Thank you.

Author: Lothar Miller (lkmiller) (Moderator)
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Glen wrote:
> I am not very familiar with timing analysis
In such a simple design you should not need this tool at all.
Lets lokk at this here:
s_PWM_int  <= std_logic_vector(unsigned(v_PWMvalue) * to_unsigned(i_PWM_Freq_Devider / 100, 9)); -- Timing Fails
You like to cast and convert you to death?
Why not doing the whole internal calculation in integer?

Beside that moaning about formalisms your problem is this:
i_PWM_Freq_Devider / 100
Here you invoke a combinatorial divider. Its eating up lots of 
ressources and addtitionally such a thing is really, really, really slow 
because it has lots of logic stages behind each other.

Its strongly not recommended to use a divider on hardware. The only 
"simple" dividers are those like 2, 4, 8, 16, 32, ...32768, 65536, ... 
because these power of two vlaues are just a little rewiring on the 

So lets pack it togehter: a number like 10 or 100 or 1000 is only good 
for man, not for computers.

If you ABSOLUTELY want to kepp on with your 100% scale i would try that:
s_PWM_int  <= std_logic_vector(unsigned(v_PWMvalue) * to_unsigned((i_PWM_Freq_Devider*4100/100)/4096, 9)); -- a little bit "uprounding" here... 
In that way I dealt the division by a "none power of two value" against 
a (fast and uncritical) multiplication and a division by a power of two. 
Try it...

And one thing more a beginner MUST use only 1 clock in his designs. A 
pro will TRY to use only 1 clock in his design.

: Edited by Moderator
Author: Glen (Guest)
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Thanks for the response.

This module is just one sub module.I had constraints with other modules 
which have been resolved. The FPGA runs on only one clock. But few other 
clocks have been generated to support other modules.

I was not aware about the division strategy in FPGAs. It makes sense. I 
tried incorporating it. Unfortunately, it did not help. The negative 
slack has just increased more. I am not sure if it requires more latency 
or I should pipeline further to reduce the slack.

Author: Glen (Guest)
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It worked when I removed 100 from the divisor. Thanks a lot. But the 
module with 150MHz clock still gives negative slack. Though, the same 
calculation is used there (which I changed to the you suggested), it 
doesnt help.

The latch points where there is negative slack are s_PWMCounter and 
v_updatePWM value.


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