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Forum: FPGA, VHDL & Verilog Multiple posedges in sensitivity list


Author: Joe (Guest)
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I have 2 signals that I need to trigger off of...at the rising edge of 
the first, I need to toggle a bit, and at the rising edge of the second, 
I need to toggle it again.  I have cut the code down to the minimum 
needed to demonstrate the problem:
module gen_reset_gate (
CLOCK_50,
        cref,
        cflt,
        reset_gate
);

input CLOCK_50
input cref;
input cflt;
output reset_gate;

reg   reset_state;

always @(posedge cref)// or posedge cflt)
  begin
    reset_state=!reset_state;
  end

  assign reset_gate = reset_state;
endmodule

It works as-is just triggering off positive edge of cref, or positive 
edge of cflt, but when I remove the comment in the always block and try 
to trigger off either rising edge, it does nothing.  Simulation verifies 
it does nothing, and my development board verifies it does nothing.

I am new to Verilog, so sorry if this is a basic question.

Author: Lattice User (Guest)
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Simulation does nothing, because reset_state is not initialized. And 
negate an unknown value will yield an unknown value.

Hardware does nothing, because the synthesizer uses the sensitivity list 
only to infer flip-flops and ignores it if you don't follow the required 
coding style. Also a flip-flop with two clock inputs doesn't exist in a 
fpga.

Author: Joe (Guest)
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Ok, so I'm trying to wrap my mind around what the required coding style 
is.  I can't find any examples to do what I'm trying to do, which is set 
an output (reset_gate) at the first rising edge (cref), then clear it at 
the second rising edge (cflt).

Any constructive help other than you're not doing it right would be much 
appreciated.

Author: Klakx (Guest)
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Can you show the solution in a schematic of digital Elements?

Author: Joe (Guest)
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Alright, I got it, in case it will help anyone, here's what I did 
(probably still not in the aforementioned coding style):
module gen_reset_gate (
        cref,
        cflt,
        reset_gate
);

input cref;
input cflt;
output reset_gate;

reg   reset_state1;
reg  reset_state2;

always @(posedge cref)
  begin
    reset_state1=!reset_state1;
    
  end
  
always @(posedge cflt)
  begin
    reset_state2=!reset_state2;
  end
  
  assign reset_gate = reset_state1 ^ reset_state2;
  
endmodule


Author: bko (Guest)
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Lattice User wrote:

>
> Hardware does nothing, because the synthesizer uses the sensitivity list
> only to infer flip-flops and ignores it if you don't follow the required
> coding style. Also a flip-flop with two clock inputs doesn't exist in a
> fpga.
Ok for VHDL but -
not correct for verilog, coding for a flipflop with async reset
see e.g:
http://www.asic-world.com/examples/verilog/d_ff.html

Author: Lattice User (Guest)
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bko wrote:
> Lattice User wrote:
>
>>
>> Hardware does nothing, because the synthesizer uses the sensitivity list
>> only to infer flip-flops and ignores it if you don't follow the required
>> coding style. Also a flip-flop with two clock inputs doesn't exist in a
>> fpga.
> Ok for VHDL but -
> not correct for verilog, coding for a flipflop with async reset
> see e.g:
> http://www.asic-world.com/examples/verilog/d_ff.html

This is the coding style for a dff with an async reset. Remove the
 if (~reset) begin
from the body, and you will get a synthesis error. But you don't get a 
ff with two clock inputs.

@Joe
There are no coding style issue with your last code. (apart with my 
personal opinion that old module style declaration should be outlawed)

It will however still have some issues.
If on powerup the two state registers will have different values, your 
output is inverted. This depends on the actual FPGA family.

Also it is very sensitive to spikes on the two inputs, assuming they 
come from the outside.

Better would be to synchronise the two inputs to your system clock, and 
use edge detection.
reg [2:0] sync_cref;
wire edge_cref;
always @(posedge sys_clk) sync_cref <= { sync_cref[1:0], cref} ;
assign edge_cref = sync_cref[1] & ~sync_cref[2];
On the edge for one signal you then can set your output to 1, and on the 
edge for the other signal reset it to 0. This solves both issues.

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