EmbDev.net

Forum: FPGA, VHDL & Verilog GPS to FPGA to PC


Author: Yuniarto Wimbo Nugroho (wimbo)
Posted on:

Rate this post
0 useful
not useful
Hello
i want send data NMEA from GPS to FPGA and from FPGA to PC, i'm using 
UART vhdl with 38400 baudrate.

i test uart with send n receive data, if i send data one alphabet 
example "a" or one number example "8" uart is work, but if i send data 
nmea from GPS like "$GPVTG,054.7,T,034.4,M,005.5,N,010.2,K*48" i cant 
receive it in my PC.

any help me please.
Thanks a lot.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Yuniarto Wimbo N. wrote:
> Hello i want send data NMEA from GPS to FPGA and from FPGA to PC, i'm
> using UART vhdl with 38400 baudrate.
Why the FPGA? I would connect the GPS directly to the PC...

> i test uart
Which one?

> i test uart with send n receive data, if i send data one alphabet
> example "a" or one number example "8" uart is work
How did you find that out?
And how did you test it?
Did you test this uart an a testbench in a simulator?

> but if i send data nmea from GPS like
> "$GPVTG,054.7,T,034.4,M,005.5,N,010.2,K*48" i cant receive it in my PC.
This somehow curios design seems to be extremely simple to me. In VHDL 
it will be somewhat like that:
  PCout  <= GPSin;
  GPSout <= PCin;

> any help me please.
Without knowing anything about your desgin, even not seeing one line of 
HDL, how should anyone be able to help?

Author: Achim S. (Guest)
Posted on:

Rate this post
0 useful
not useful
so a single character works, but a sequence of characters is not 
received? Does "not received" mean, that you get no data at all or do 
you receive scrambled data?

Maybe you send the individual characters of your NMEA-string too close 
to each other, so that there's not enough time for a stop-bit inbetween. 
Take a look to the bit-sequence with an oscilloscope and decode the 
first 2-3 characters manually, that may tell you what you have to fix.

Author: Yuniarto Wimbo Nugroho (wimbo)
Posted on:

Rate this post
0 useful
not useful
>Why the FPGA? I would connect the GPS directly to the PC...
-because i want made autopilot system using FPGA

>How did you find that out?
>And how did you test it?
>Did you test this uart an a testbench in a simulator?
- i find result di my pc
- i test fpga to pc using

this is my uart
 TX Modul:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TX is
port(s_out:out std_logic;
    p_in:in std_logic_vector(7 downto 0);
    go:in std_logic;
    clk:in std_logic);
end TX;

architecture UARTtx of TX is
signal clk9600:std_logic:='0';
begin
  process(clk)
  variable count:integer range 0 to 1300:=0;
  begin
    if clk='1' and clk'event then 
      if count>=650 then count:=0;clk9600<=not clk9600;
      else count:=count+1;
      end if;
    end if;
  end process;
  process(clk9600,go,p_in)
  variable cnt:integer range -2 to 90:=0;
  variable buf:std_logic_vector(9 downto 0):="1010000010";
  variable stop:std_logic;
  begin
    if clk9600='1' and clk9600'event then 
      if go='1' then
        buf(8 downto 1):=p_in;
        if cnt=0 then s_out<='0';cnt:=1;
        elsif cnt=1 then s_out<=p_in(0);cnt:=2;
        elsif cnt=2 then s_out<=p_in(1);cnt:=3;
        elsif cnt=3 then s_out<=p_in(2);cnt:=4;
        elsif cnt=4 then s_out<=p_in(3);cnt:=5;
        elsif cnt=5 then s_out<=p_in(4);cnt:=6;
        elsif cnt=6 then s_out<=p_in(5);cnt:=7;
        elsif cnt=7 then s_out<=p_in(6);cnt:=8;
        elsif cnt=8 then s_out<=p_in(7);cnt:=9;
        elsif cnt=9 then s_out<='1';
        end if;
      else cnt:=0;
      end if;
    end if;
  end process;
end UARTtx;


RX Modul:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity RX is
port(s_in:in std_logic;
    p_out:out std_logic_vector(7 downto 0):=X"00";
    clk:in std_logic);
end RX;
architecture UARTs of RX is
signal cnt:integer range 0 to 25:=0;
signal buff:std_logic_vector(7 downto 0):=X"00";
signal start:std_logic:='0';
signal clk9600:std_logic:='0';
begin
  process(clk)
  variable count:integer range 0 to 1300:=0;
  begin
    if clk='1' and clk'event then 
      if count>=650 then count:=0;clk9600<=not clk9600;
      else count:=count+1;
      end if;
    end if;
  end process;
  process(s_in,clk9600,cnt)  
  begin
    if clk9600='0' and clk9600'event then 
      if cnt>=9 and s_in='1' then cnt<=0;
      --if cnt>=9 and s_in='0' then cnt<=0;
      elsif start='1' and cnt<=20 then cnt<=cnt+1;
      end if;
    end if;
    
    if s_in='0' and cnt=0 then start<='1';
    elsif cnt>=9 and s_in='1' then start<='0';
    --elsif cnt>=9 and s_in='0' then start<='0';
    end if;  
  end process;
  process(s_in,cnt,clk9600)  
  begin
    if cnt>=1 and cnt<=8 and clk9600='1' then
      buff(cnt-1)<=s_in;
    end if;    
  end process;
  p_out<=buff when start='0';  
  --p_out<=X"F0";
end UARTs;

: Edited by Moderator
Author: Yuniarto Wimbo Nugroho (wimbo)
Posted on:

Rate this post
0 useful
not useful
>so a single character works, but a sequence of characters is not
>received? Does "not received" mean, that you get no data at all or do
>you receive scrambled data?

>Maybe you send the individual characters of your NMEA-string too close
>to each other, so that there's not enough time for a stop-bit inbetween.
>Take a look to the bit-sequence with an oscilloscope and decode the
>first 2-3 characters manually, that may tell you what you have to fix.

yes you true, i have receive scramble data, and data not constants per 
second

: Edited by User
Author: Achim S. (Guest)
Posted on:

Rate this post
0 useful
not useful
ok, some problems to start with:

- you use a logic signal (clk9600) as a clock. Don't do that. Take the 
real clock clk instead to toggle your registers and use a Clock-Enable 
to define the baudrate.

- for your transmitter I see a shift-register, but I do not yet see a 
UART yet. E.g. your code will only give you a correct sequence when the 
signal "go" is 1 for exactly 10 bittimes. How is the signal "go" 
controlled? If if toggles back to 0 to early, the remaining bits are 
skipped. If it toggles to 0 to late, the transmission is restarted.

- in your receiver you use a latch to store incoming data. Don't do 
that: work with registers. Furthermore the moment, when you finally 
store the data to buff, is not fixed to the middle of the bit-time. The 
clk9600 of the receiver must somehow be synchronized to the begin of the 
startbit.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

Rate this post
0 useful
not useful
Yuniarto Wimbo N. wrote:
> this is my uart
1. See the screenshot.
2. Read it and understand it.
2. Do it.


There are too much signals in the sensitivity list:
>   process(clk9600,go,p_in)
clk9600 would be enough.
But: clk9600 ist NOT a clock, is is just a simple clock enable...

> i have receive scramble data, and data not constants per second
As I saw that code my first thought was: Ouch!

You MUST implement a test bench an check your design on that test bench. 
Then you can see that whole bunch of tricky race conditions in your 
code. One is e.g. the sampling point of the incoming RS232 signal.

At the last link there you can find a test bench:
http://www.lothar-miller.de/s9y/archives/60-RS232-...
And also look there:
http://www.lothar-miller.de/s9y/categories/42-RS232
(Try Google translator, its German...)

: Edited by Moderator
Author: Yuniarto Wimbo Nugroho (wimbo)
Posted on:

Rate this post
0 useful
not useful
>Achim S. (Guest)
(clk9600) is just name only not value baudrate. :D
thanks a lot for your guide, ok i want correct my programming again.
:D

Author: Yuniarto Wimbo Nugroho (wimbo)
Posted on:

Rate this post
0 useful
not useful
> Lothar Miller
i'm sorry about my post :) please forgive me about it.

ok i'll implement uart vhdl programming in testbench.

Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

Rate this post
0 useful
not useful
Yuniarto Wimbo N. wrote:
> (clk9600) is just name only
But you use it as a clock, because everything using a 'event or a 
rising_edge() or a falling_edge() is a clock...  :-o

Some simple rules for beginners:
- only 1 clock in the whole design (thats usually around 10..100MHz)
- external signals must be synced to that clock before using them
- no variables, or at the very least no memorizing variables
- no latches (read the synthesizers warnings!)

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.