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Forum: FPGA, VHDL & Verilog Please Help! Not gate implementation nand


Author: Mihai Marius (mike999)
Posted on:

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Hello everybody! I need some help. I use VHDL language and ModelSim PE 
Student Edition. I nade to build some elementary gates: not, or, xor, 
and, mux mux, dmux, 16 bit variants not16 and16 and multiway variants 
mux8way16 etc from nand gates. I made some schematics on paper and 
logic. Ex. Not imp. Nand : (a Nand b) Nand (a Nand b).
My first gate i want to buils is Not gate. (a nand a), for this i make 
this code:
library IEEE;
use ieee.std_logic_1164.all;

entity noot is
         port (a : in std_logic;
               cout : out std_logic
              );
end noot;

architecture behavior of noot is
          component naand
           port(
                a1 : in std_logic;
                b1 : in std_logic;
               );
          end component;

     NA1 : naand port map (
                a1 =>a,
                b1 =>a,
                out1 => cout
                );
so here is my problem, how i can do the function of nand?
it was simple to write:
 
 cout<= a nand a; 
but i want later to add more nand gates in separate bloks
i try with signal
signal s1, s2 : std_logic := '0'; or without ":= '0'"
 NA1 : naand port map (
                a1 =>s1,
                b1 =>s2,
                out1 => cout => s1 nand s2
                );
How i can make this to work?

This is schematic of wat i want:
           
                        NOT GATE
            ____________________________      
           |            ________        |     
           |      _____|        \       |
    a      |     /     |         \      |  cout
-----------|----=      |   NAND   |-----|-------
           |     \_____|         /      |
           |           |________/       |
           |____________________________|


: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:
Attached files:

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Mihai M. wrote:
> I use VHDL language
Pls have a look at the screenshot...

> component naand
That component has no output. Its useless and will be optimized away.

> out1 => cout => s1 nand s2
What should this do?
In a port map you ca assign 1 port to 1 signal.
> How i can make this to work?

> This is schematic of wat i want
I'm not able to figure out your problem... :-/

> so here is my problem, how i can do the function of nand?
Try it this way and think about it...
library IEEE;
use ieee.std_logic_1164.all;

entity naand is
         port (a1,b1 : in std_logic;
               out1 : out std_logic);
end noot;

architecture behavior of naand is
begin
    out1 <= a1 nand b1;
end behavior;



library IEEE;
use ieee.std_logic_1164.all;

entity noot is
         port (a : in std_logic;
               cout : out std_logic
              );
end noot;

architecture behavior of noot is
     component naand
         port (a1,b1 : in std_logic;
               out1 : out std_logic);
     end component;

     NA1 : naand port map (
                a1 => a,
                b1 => a,
                out1 => cout
                );
end behavior;

Author: Mihai Marius (mike999)
Posted on:

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Well,  i want to make that component naand to function like a nand gate, 
thx for the information.

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