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Forum: FPGA, VHDL & Verilog Please Help! Not gate implementation nand


Please Help! Not gate implementation nand
von Mihai M. (mike999)

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Hello everybody! I need some help. I use VHDL language and ModelSim PE 
Student Edition. I nade to build some elementary gates: not, or, xor, 
and, mux mux, dmux, 16 bit variants not16 and16 and multiway variants 
mux8way16 etc from nand gates. I made some schematics on paper and 
logic. Ex. Not imp. Nand : (a Nand b) Nand (a Nand b).
My first gate i want to buils is Not gate. (a nand a), for this i make 
this code:
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library IEEE;

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use ieee.std_logic_1164.all;

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entity noot is

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         port (a : in std_logic;

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               cout : out std_logic

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              );

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end noot;

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architecture behavior of noot is

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          component naand

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           port(

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                a1 : in std_logic;

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                b1 : in std_logic;

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               );

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          end component;

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     NA1 : naand port map (

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                a1 =>a,

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                b1 =>a,

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                out1 => cout

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                );

so here is my problem, how i can do the function of nand?
it was simple to write:
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 cout<= a nand a;

but i want later to add more nand gates in separate bloks
i try with signal
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signal s1, s2 : std_logic := '0'; or without ":= '0'"

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 NA1 : naand port map (

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                a1 =>s1,

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                b1 =>s2,

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                out1 => cout => s1 nand s2

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                );

How i can make this to work?

This is schematic of wat i want:
1
           

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                        NOT GATE

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            ____________________________      

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           |            ________        |     

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           |      _____|        \       |

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    a      |     /     |         \      |  cout

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-----------|----=      |   NAND   |-----|-------

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           |     \_____|         /      |

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           |           |________/       |

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           |____________________________|


  


  



  

  
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    Re: Please Help! Not gate implementation nand
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

      

      

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Mihai M. wrote:
> I use VHDL language
Pls have a look at the screenshot...

> component naand
That component has no output. Its useless and will be optimized away.

> out1 => cout => s1 nand s2
What should this do?
In a port map you ca assign 1 port to 1 signal.
> How i can make this to work?

> This is schematic of wat i want
I'm not able to figure out your problem... :-/

> so here is my problem, how i can do the function of nand?
Try it this way and think about it...
1
library IEEE;

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use ieee.std_logic_1164.all;

3
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entity naand is

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         port (a1,b1 : in std_logic;

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               out1 : out std_logic);

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end noot;

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architecture behavior of naand is

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begin

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    out1 <= a1 nand b1;

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end behavior;

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library IEEE;

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use ieee.std_logic_1164.all;

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entity noot is

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         port (a : in std_logic;

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               cout : out std_logic

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              );

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end noot;

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architecture behavior of noot is

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     component naand

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         port (a1,b1 : in std_logic;

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               out1 : out std_logic);

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     end component;

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     NA1 : naand port map (

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                a1 => a,

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                b1 => a,

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                out1 => cout

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                );

36
end behavior;


  


  




  

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    Re: Please Help! Not gate implementation nand
  


  

    

      von
      
        Mihai M.
        (mike999)
        
      
      


      
    


    

      
    

    

    

  
  


  

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Well,  i want to make that component naand to function like a nand gate, 
thx for the information.

  


  




  

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