Forum: FPGA, VHDL & Verilog RAM testing using VHDL

Author: Ritu Singh (Company: student) (ritu_singh)
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HELLO.. everyone i ll be very thankful if u ll be able to help me ... i 
m a student, and i am working on RAM testing i need info about it .. i 
only know what faults are possible within the RAM and what is memory 
structure as i am a beginner please provide regarding information about 
it ..i am uploading my base paper and as i am trying to create a new 
algorithm which covers all faults as possible..and speed up the testing 

please provide information


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