Forum: FPGA, VHDL & Verilog CAN controller implementation using FPGA

Author: CJU (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello, everyone.

First, i'm sorry. Because of, I cant speak english well.

I have some ploblem about my project.

I should design CAN controller using Verilog HDL in FPGA.

But, any web-site doesn't have that information.

I got the CAN verilog code in OpenCore.

But, I cant understand OpenCore code.

It explain only block diagram....

If you know about that.... help me please..

Thank you very much.

Author: CJU (Guest)
Posted on:

Rate this post
0 useful
not useful
And, I used xilinx ISE tool and simulator

Author: mh (Guest)
Posted on:

Rate this post
0 useful
not useful
Unfortunately CAN specs are ISO standard and not freely available (any 
At Bosch you can still find some documents --> 

What is exactly your problem? The CAN bus or Verilog?

If you shall design an CAN IP core, you should do that based on the 
specification not based on another implementation (with missing 
documentation and questionable quality).
The person that gave you the task should also provide access to the 
corresponding specification (ISO11898*).

Author: CJU (Guest)
Posted on:

Rate this post
0 useful
not useful
First, Thank you very much, your reply.

I have to make CAN controller using Verilog HDL Code. And, 
implementation in FPGA.

So, I downloaded the code in OpenCore and simulated using Xilinx ISE 
But, I cant find output and input... in simulation.. cant understand 
that code.

I need some code(CAN controller in Verilog) or CAN block example(Verilog 
code.. bit stuffing, CRC...etc)

If you know the solution about my ploblem, tell me please..

Thank you!

Author: Tim (Guest)
Posted on:

Rate this post
0 useful
not useful

I had the same problem a while ago. I also used the code by 
opencores.org but Vivado instead of ISE.
What exactly do you mean with input and outputs? You have a Wishbone bus 
as input (registers are the same as SJA1000 controller) and CAN-rx and 
tx as output.

I recently posted my solution: 


Author: CJU (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello, Tim. Thank you your reply.

First, input and output mean just signal in verilog
(ex, CAN module (
   input [15:0] in,
   output reg [15:0] out

I cant find that in Opencore codes.

Did you design the CAN controller in FPGA?
( using Opencore code or another method...)

I have a ZYNQ board for FPGA design.
If you implemented CAN controller in FPGA, Can you help me?

And, also Can I know your email address?

If i can know your email address, send ma a message to 

Thank you very much, Tim.


Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]

Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.