Forum: FPGA, VHDL & Verilog Voltage ThrEshold Adaptive Memristor in verilog

Author: Ronny Josef (Company: Student) (ra_auu)
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Hello guys
I am a beginner with Verilog HDL and trying to write a verilog code to 
Voltage ThrEshold Adaptive Memristor VTEAM

I began to modify the VTEAM memristor model proposed by Sahar Kvatinsky 
in 2012 but I dont get the same results when I simulate my model in 
Cadence Virtuoso. I'm not interested in windowing functions because I 
want to simulate it only with ideal window

It is a part of my project and I will be very thankful if someone helps 
me. I attached my verilog module in a dat file if you wants to look at 
my code and advice me to the right way

Best regards


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