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Forum: FPGA, VHDL & Verilog Does Verilog have generic map like VHDL?


Author: Sean Zheng (Guest)
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I am a beginner of Verilog. I am trying to build an N-bit-comparator. 
But I found no information for any generic map. I know in VHDL I can do

generic (N: integer:=4);

so that I can modify bits when I want to use this block.

If there is anything in Verilog that is similar to generic map in VHDL, 
it will help save me lots of work.

Author: Tim (Guest)
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googled: verilog generic

http://www.asic-world.com/verilog/para_modules1.html

sufficient explaination for you?

Author: Lattice User (Guest)
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It is called parameter
module Sample #(parameter Width=8) (input wire [Width-1:0] DataIn)

Instanziated it is like this:
wire [11:0] Data;
Sample #(.Width(12)) InstanceName (.DataIn( Data ));

Author: Sean Zheng (Guest)
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Thank you! My problem's solved now!

Author: Sean Zheng (Guest)
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@Lattice, Thank you! Now I understand very clear!

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