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Forum: FPGA, VHDL & Verilog looking for 16 bits adder in vhdl


Author: Maxim Moor (max_min)
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i need a vhdl code to add 16  bits registers

Author: Klaus (Guest)
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Most synthesizers will instantiate adder structures if you write:

library ieee;
use ieee.numeric_std.all;

signal a: unsigned(8 downto 0); 0 to 2**9-1
signal b: unsigned(7 downto 0); 0 to 2**8-1
signal b: unsigned(7 downto 0); 0 to 2**8-1

a <= b + c;



Note, that the signal a, holding the result, must be one bit wider than 
the signals holding operands.

Consider - which means read about - using the packages numeric_std (in 
contrast to std_logic_vector).

In case you want to see explicit code of an adder, search the internet. 
I am not sure, but I assume that somebody posted such code just for 
educational purposes.

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