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what's problem this top&design
von frowerwolrd (Guest)

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module diceroll(

2
  input    wire           CLK,

3
  input    wire           RST,

4
  input    wire           roll,

5
  output   wire   [2:0]   dice1,

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  output   wire   [2:0]   dice2

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);

8
  

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  reg [7:0] lfsr1;

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  reg [4:0] lfsr2;

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  wire [7:0] temp1;

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  wire [4:0] temp2;

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  assign temp1 = lfsr1 % 6 + 1;

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  assign temp2 = lfsr2 % 6 + 1;

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  assign dice1 = (roll) ? temp1[2:0] : 3'b000;

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  assign dice2 = (roll) ? temp2[2:0] : 3'b000;  

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  always @ (posedge CLK or posedge RST)

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    begin

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      if(RST)

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        lfsr1 <= 8'b00000001;

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      else

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        begin

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          lfsr1[0] <= lfsr1[3] ^ lfsr1[4] ^ lfsr1[5] ^ lfsr1[7];

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          lfsr1[1] <= lfsr1[0];

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          lfsr1[2] <= lfsr1[1];

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          lfsr1[3] <= lfsr1[2];

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          lfsr1[4] <= lfsr1[3];

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          lfsr1[5] <= lfsr1[4];

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          lfsr1[6] <= lfsr1[5];

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          lfsr1[7] <= lfsr1[6];

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        end

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    end

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  always @ (posedge CLK or posedge RST)

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    begin

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      if(RST)

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        lfsr2 <= 5'b00001;

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      else

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        begin

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          lfsr2[0] <= lfsr2[4] ^ lfsr2[2];

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          lfsr2[1] <= lfsr2[0];

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          lfsr2[2] <= lfsr2[1];

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          lfsr2[3] <= lfsr2[2];

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          lfsr2[4] <= lfsr2[3];

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        end

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    end

49
  

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endmodule

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module dice_top (

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    input   wire            CLK,

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    input   wire            RST,

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    input   wire            Rb,

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    output  reg     [2:0]   dice1,

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    output  reg     [2:0]   dice2,

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    output  reg             win,

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    output  reg             lose

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);

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    wire    [2:0]   a;

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    wire    [2:0]   b;

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    wire            roll;

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    wire            win_w;

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    wire            lose_w;

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    always @*

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    begin

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        dice1<=a;

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        dice2<=b;

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        win<=win_w;

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        lose<=lose_w;

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    end

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    DICE    top  (

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        .CLK        (CLK),

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        .RST        (RST),

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        .dice1      (a),

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        .dice2      (b),

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        .Rb         (Rb),

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        .win        (win_w),

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        .lose       (lose_w),

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        .roll       (roll)

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    );

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    diceroll      dice(

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        .CLK        (CLK),

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        .RST        (RST),

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        .roll       (roll),

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        .dice1      (a),

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        .dice2      (b)

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    );

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endmodule

Error-[URMI] Unresolved modules
testbench.sv, 27
"DICE top( .RST (RST),  .CLK (CLK));"
  Module definition of above instance is not found in the design.

1 error

I DO NOT known..

  


  



  

  
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    Re: what's problem this top&design
  


  

    

      von
      
        Lothar M.
            (Company: Titel)
        (lkmiller)
        (Moderator)
      
      


      
    


    

      
    

    

    

  
  


  

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frowerwolrd wrote:
> Module definition of above instance is not found in the design.
I'm not the Verilog man, but the toolchain seems to be right: there is 
no "module top". So try a "dice_top" instead the "top"...


And try that:
1
[c]

2
   Verilog Code

3
[/c]

You'll get syntax highlight for free...

  


  



  

  
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    Re: what's problem this top&design
  


  

    

      von
      
        Lattice User (Guest)
      
      


      
    


    

      
    

    

    

  
  


  

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Lothar M. wrote:
> frowerwolrd wrote:
>> Module definition of above instance is not found in the design.
> I'm not the Verilog man, but the toolchain seems to be right: there is
> no "module top". So try a "dice_top" instead the "top"...
>

In Verilog the order is module name followed by instance name. The 
missing module is named DICE, a simple name change won't help here.
Keep in mind Verilog is case sensitive.

  


  




  

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