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Author: frowerwolrd (Guest)
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module diceroll(
  input    wire           CLK,
  input    wire           RST,
  input    wire           roll,
  output   wire   [2:0]   dice1,
  output   wire   [2:0]   dice2
);
  
  reg [7:0] lfsr1;
  reg [4:0] lfsr2;
  wire [7:0] temp1;
  wire [4:0] temp2;
  
  assign temp1 = lfsr1 % 6 + 1;
  assign temp2 = lfsr2 % 6 + 1;
  assign dice1 = (roll) ? temp1[2:0] : 3'b000;
  assign dice2 = (roll) ? temp2[2:0] : 3'b000;  

  always @ (posedge CLK or posedge RST)
    begin
      if(RST)
        lfsr1 <= 8'b00000001;
      else
        begin
          lfsr1[0] <= lfsr1[3] ^ lfsr1[4] ^ lfsr1[5] ^ lfsr1[7];
          lfsr1[1] <= lfsr1[0];
          lfsr1[2] <= lfsr1[1];
          lfsr1[3] <= lfsr1[2];
          lfsr1[4] <= lfsr1[3];
          lfsr1[5] <= lfsr1[4];
          lfsr1[6] <= lfsr1[5];
          lfsr1[7] <= lfsr1[6];
        end
    end
  
  always @ (posedge CLK or posedge RST)
    begin
      if(RST)
        lfsr2 <= 5'b00001;
      else
        begin
          lfsr2[0] <= lfsr2[4] ^ lfsr2[2];
          lfsr2[1] <= lfsr2[0];
          lfsr2[2] <= lfsr2[1];
          lfsr2[3] <= lfsr2[2];
          lfsr2[4] <= lfsr2[3];
        end
    end
  
endmodule

module dice_top (
    input   wire            CLK,
    input   wire            RST,
    input   wire            Rb,
    output  reg     [2:0]   dice1,
    output  reg     [2:0]   dice2,
    output  reg             win,
    output  reg             lose

);
    wire    [2:0]   a;
    wire    [2:0]   b;
    wire            roll;
    wire            win_w;
    wire            lose_w;

    always @*
    begin
        dice1<=a;
        dice2<=b;
        win<=win_w;
        lose<=lose_w;
    end
    
    DICE    top  (
        .CLK        (CLK),
        .RST        (RST),
        .dice1      (a),
        .dice2      (b),
        .Rb         (Rb),
        .win        (win_w),
        .lose       (lose_w),
        .roll       (roll)
    );
            
    diceroll      dice(
        .CLK        (CLK),
        .RST        (RST),
        .roll       (roll),
        .dice1      (a),
        .dice2      (b)
    );

endmodule
Error-[URMI] Unresolved modules
testbench.sv, 27
"DICE top( .RST (RST),  .CLK (CLK));"
  Module definition of above instance is not found in the design.

1 error

I DO NOT known..

: Edited by Moderator
Author: Lothar Miller (lkmiller) (Moderator)
Posted on:

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frowerwolrd wrote:
> Module definition of above instance is not found in the design.
I'm not the Verilog man, but the toolchain seems to be right: there is 
no "module top". So try a "dice_top" instead the "top"...


And try that:
[c]
   Verilog Code
[/c]
You'll get syntax highlight for free...

: Edited by Moderator
Author: Lattice User (Guest)
Posted on:

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Lothar M. wrote:
> frowerwolrd wrote:
>> Module definition of above instance is not found in the design.
> I'm not the Verilog man, but the toolchain seems to be right: there is
> no "module top". So try a "dice_top" instead the "top"...
>

In Verilog the order is module name followed by instance name. The 
missing module is named DICE, a simple name change won't help here.
Keep in mind Verilog is case sensitive.

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