EmbDev.net

Forum: FPGA, VHDL & Verilog Re: Verilog project


Author: Joe Joe (Guest)
Posted on:

Rate this post
0 useful
not useful
Hello All I have multiple questions for a project for school I am 
currently using the Nexys 2 board I have to create a traffic light 
controller. I was wondering about a few things that my teacher did not 
go over.
The first one is: How do you make multiple LEDs blink such that it would 
repeat in a traffic light simulation such as 5 seconds red, 3 seconds 
yellow, 1 second green.

My second question is how do you get a countdown to be displayed on the 
seven segment display on a Nexys 2 board?

my third question is how do you use the enable line in the program?

This is the code I have so far
// Joseph Abel
// display same as Y
// bits  same as L 
module Top_Mod(clk,enable,reset,display,bits);

  input clk,reset,enable;
  output [6:0] display;
  output[3:0] bits;
  
  wire[2:0] num;
  wire[7:0]output_val;
  wire[3:0] sev;
  wire[6:0] display_val;
  wire clock;
  output_result O2(output_val,num,clock);
  multiplexing M3(sev,bits,clock,output_val[7:4],output_val[3:0]);
  Seven_segment S4(display_val, sev);
  clockslow C5(clk,clock,reset);
  
  assign display= display_val;
  
endmodule

module multiplexing(seg, light, clock, M ,L);
    input clock;
    input [3:0] M;
    input [3:0] L;
    
    output reg [3:0] seg;
    output reg[3:0] light;
    reg select;
    
    always @(clock)// generates a signal that performs multiplexing 
      begin
      select=~clock;
      end
      
      always @(clock)
        case(select) // display MSB when select=0
      0:
      begin 
            select =M;
            light=4'b1110; 
        end
        
      1: 
      begin
      
        select=L;
        light= 4'b1101;
        
      end 
      endcase
      
endmodule

module Seven_segment(seven,val);
  input [3:0] val;
  output reg[6:0] seven;
    always @(val)
    begin
          case(val)
          0  : seven= 7'b1000000;
          1  : seven= 7'b1111001;
          2  : seven= 7'b0100100;
          3  : seven= 7'b0110000;
          4  : seven= 7'b0011001;
          5  : seven= 7'b0010010;
          6  : seven= 7'b0000010;
          7  : seven= 7'b1111000;
          8  : seven= 7'b0000000;
          9  : seven= 7'b0011000;
          default : seven=7'b1000000;
        endcase
      end
endmodule
[\vhdl]

[vhdl]
module clockslow(clk, clkreturn,reset);

input clk,reset;
output clkreturn;
wire clk_50Mhz;
wire clk_100000hz;
wire clk_10000hz;
wire clk_1000hz;
wire clk_100hz;
wire clk_10hz;
wire clk_1hz;

assign clkreturn= clk_1hz;

divide_50 d6(clk_50Mhz,clk,reset);
divide_10 d5(clk_100000hz,clk_50Mhz,reset);
divide_10 d4(clk_10000hz,clk_1000000hz,reset);
divide_10 d3(clk_1000hz,clk_10000hz,reset);
divide_10 d2(clk_100hz,clk_1000hz,reset);
divide_10 d1(clk_10hz,clk_100hz,reset);
divide_10 d0(clk_1hz,clk_10hz,reset);

endmodule

module divide_50(outro, new_clk,new_reset );
  input new_clk, new_reset;
  output reg outro;
    reg[4:0] counter;
      always @(posedge new_clk or posedge new_reset)
        begin
          if(new_reset)
            begin
              outro<= 1'b0;
              counter<= 5'b00000;
            end
          else if(counter <24)
          begin
            counter <=counter+1'b1;
          end
        else
          begin
            counter<=5'b00000;
            outro<=~outro;
          end
        end
endmodule

module divide_10(outro2,new_clk,new_reset);
  input new_clk,new_reset;
  output reg outro2;
  reg[2:0] counter;
    always@(posedge new_clk or posedge new_reset)
      begin
        if(new_reset)
          begin
            outro2<=1'b0;
            counter <=3'b000;
          end
        else if(counter<4)
          begin
            counter <= counter+ 1'b1;
          end
        else
          begin
            counter <=3'b000;
            outro2<=~outro2;
          end
        end

endmodule

module output_result(out,new_val,clk);
    output reg[7:0]out;
   input [2:0] new_val;
   input clk;
   
   always@(posedge clk)
    begin 
      out=out+new_val;
      if(out>99)
        out= 8'b00000000;
      end
    
   
endmodule

My pin config isbelow
NET"enable" LOC= "G18";
NET"enable" LOC= CLOCK_DEDICATED_ROUTE=FALSE;
NET "clk" LOC= "B8";
NET "reset" LOC= "H13";

NET "display[0]" LOC = "L18";
NET "display[1]" LOC = "F18";
NET "display[2]" LOC = "D17";
NET "display[3]" LOC = "D16";
NET "display[4]" LOC = "G14";
NET "display[5]" LOC = "J17";
NET "display[6]" LOC = "H14";

NET "bits[3]" LOC = "F17";
NET "bits[2]" LOC = "H17";
NET "bits[1]" LOC = "C18";
NET "bits[0]" LOC = "F15";

Author: Alexx (Guest)
Posted on:

Rate this post
0 useful
not useful
You can solve your Task using a finite state machine!
I´m just learning VHDL so i cant help u with ur verilog code, but this 
task should be realy easy with a state machine. You youst need 5 red 
states, 3 yellow, 1 green and start at the begibnning, im sure if u 
google it you will find some examples!

Author: Joe Joe (Guest)
Posted on:

Rate this post
0 useful
not useful
I did google it but its just my teacher never went over verilog than 
gave us this project on it. But thats a good idea Ill start on that I 
also don't know whats wrong with my seven seg code

Reply

Entering an e-mail address is optional. If you want to receive reply notifications by e-mail, please log in.

Rules — please read before posting

  • Post long source code as attachment, not in the text
  • Posting advertisements is forbidden.

Formatting options

  • [c]C code[/c]
  • [avrasm]AVR assembler code[/avrasm]
  • [vhdl]VHDL code[/vhdl]
  • [code]code in other languages, ASCII drawings[/code]
  • [math]formula (LaTeX syntax)[/math]




Bild automatisch verkleinern, falls nötig
Note: the original post is older than 6 months. Please don't ask any new questions in this thread, but start a new one.