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Forum: FPGA, VHDL & Verilog Controller for Pico Processor


Author: Chris Hancock (uss_hancock)
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I'm not very good with VHDL so i was hoping someone could help me design 
a controller for a pico processor.

I have the empty architecture code as:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pico_cntrl is
Port ( clk : in std_logic; rst : in std_logic; go : in std_logic;
ir : in std_logic_vector(3 downto 0);
ld_in : out std_logic; ld_out : out std_logic;
sel : out std_logic; ld_ir : out std_logic;
ld_a : out std_logic; ld_b : out std_logic;
ld_ccr : out std_logic; ld_tmp : out std_logic);
end pico_cntrl;

architecture Behavioral of pico_cntrl is

begin

end Behavioral;.





The instruction set I am trying to impliment are ADD, SUB, AND, OR, 
CMPL, IN A, OUT A, MOV, STOP. Thanks very much!

Author: Tim (Guest)
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you are welcome... to insert your first assumptions

Author: Chris Hancock (uss_hancock)
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I was hoping that someone could help me get started. I don't know where 
to even begin .

Author: out of the mist (Guest)
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