Maxim M. wrote:
> i need your help
Usually its not the forum job to do others homework.

So lets try it this way: YOU start with something, then YOU show what 
you have and tell us what problems you encounter with it. Then WE will 
try to solve the problems together with YOU.

It seems to be a small register based CPU with 8 registers. Do you have 
the "wrapper" for that ALU (="instruction set")? Or do you have to 
implement the whole CPU core?

All in all its a fairly easy job. Good to start with VHDL and 
simulation...

really i am starting the coding, but i have an confusing in defining 
signals.
i am assuming that i have 8 signals for registers, but what is the 
length for each register? because for example instruction ADDI each 
source register and destination register is 3 bits and the immediate 
value is 7 bits?
so any starting point?

Maxim M. wrote:
> each source register and destination register is 3 bits
Those 3 bits are pointers to registers. Indeed you have 8 registers, and 
the 3 bits are the address 0..7 to one of those 8 registers. I assume it 
is a 8 bit CPU, so you have 8 registers with each 8 bit width.

A little hint: you don't have problems with VHDL at first. A HDL is a 
hardware DESCRIPTION language. And to DESCRIBE something you must have a 
picture of it. At least in mind, better on paper.

hello
here is sample of my code, is this write? any help?

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library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.numeric_std.all;

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use ieee.std_logic_arith.all;

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use ieee.std_logic_unsigned.all;

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-- Uncomment the following library declaration if using

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-- arithmetic functions with Signed or Unsigned values

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--use IEEE.NUMERIC_STD.ALL;

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-- Uncomment the following library declaration if instantiating

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-- any Xilinx primitives in this code.

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--library UNISIM;

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--use UNISIM.VComponents.all;

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entity alu is

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 generic (

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    MAXWIDTH : integer := 16;

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    MAXDEPTH : integer := 12

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  );

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end alu;

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architecture Behavioral of alu is

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-- CONSTANTS DECLARATION

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constant ADD : std_logic_vector(2 downto 0) := "000"; 

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constant ADDI : std_logic_vector(2 downto 0) := "001";

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constant NND : std_logic_vector(2 downto 0) := "010";

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constant LUI : std_logic_vector(2 downto 0) := "011"; 

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constant SW : std_logic_vector(2 downto 0) := "100"; 

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constant LW : std_logic_vector(2 downto 0) := "101";

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constant BEQ : std_logic_vector(2 downto 0) := "110"; 

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constant JALR : std_logic_vector(2 downto 0) := "111";  

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-- SIGNALS DECLARATION

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signal opcode : std_logic_vector(MAXWIDTH-1 downto MAXWIDTH-3);

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signal regA : std_logic_vector(MAXWIDTH-4 downto MAXWIDTH-6);

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signal regB : std_logic_vector(MAXWIDTH-7 downto MAXWIDTH-5);

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signal regC : std_logic_vector(MAXWIDTH-14 downto 0);

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signal imm7: std_logic_vector(MAXWIDTH-10 downto 0);

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signal imm10: std_logic_vector(MAXWIDTH-7 downto 0);

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  signal pc_reg   : std_logic_vector(MAXWIDTH-1 downto 0);

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  signal pc_next  : std_logic_vector(MAXWIDTH-1 downto 0);

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  signal ir_reg   : std_logic_vector(MAXWIDTH-1 downto 0);

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  signal ir_next  : std_logic_vector(MAXWIDTH-1 downto 0);

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  signal acc_reg  : std_logic_vector(MAXWIDTH-1 downto 0);

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  signal acc_next : std_logic_vector(MAXWIDTH-1 downto 0);

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begin

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process 

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(

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    pc_reg, pc_next,

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    ir_reg, ir_next,

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    acc_reg, acc_next

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  )

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  variable opcode_v : std_logic_vector(2 downto 0);

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  begin

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  opcode <= ir_reg(MAXWIDTH-1 downto MAXWIDTH-3);

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  regA <= ir_reg(MAXWIDTH-4 downto MAXWIDTH-6);

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  regB <= ir_reg(MAXWIDTH-7 downto MAXWIDTH-5);

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  regC <= ir_reg(MAXWIDTH-14 downto 0);

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  imm7 <= ir_reg(MAXWIDTH-10 downto 0);

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  imm10 <= ir_reg(MAXWIDTH-7 downto 0);

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  opcode_v := opcode;

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    case (opcode_v) is

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   when ADD =>

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    regA <= regB + regC;

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   when NND =>

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    regA <= regB nand regC;

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    when others =>

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        pc_next <= pc_reg;

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   end case;

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  end process;

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end Behavioral;

Maxim M. wrote:
> use IEEE.numeric_std.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
Either the first one OR the both last ones. But never ever all of them 
together.
Otherwise you will encounter some funny and extremely strange error 
messages about multiple definitions of operators and data types...

> variable opcode_v : std_logic_vector(2 downto 0);
Why a variable? You will not need a variable here, and so my my tip 
is: do not use them. You could easily write a

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    case (opcode) is ...

instead.

> any help?
The first step is done. Now you must add some kind of flesh to that 
bones.

1. At first: your ALU is very autistic. It has no input and no output. 
The input will be the instruction word. Then you will have to create a 
package that holds the register set for the 8x 16 bit registers. That 
register set is an output, so it can be read from a upper/top level 
module, but it can only be manipulated by the ALU itself.

2. I can not see any use for the *_next signals at all. The ALU itself 
is completely combinatorial, so the only clock necessary is that one to 
store the calculation results in the register set.

3. Why tricking around with generics? Your instruction format is 
strictly defined. It is 16 bits wide and will not change. So there is 
no use in defining a generic for a 18 bit or a 24 or a 13 bit format.

4. Set up a testbench for this neat project. Generate some stimuli 
vectors to test the functionality...

really i dont know how to start coding in write way.
could you help me?