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Forum: FPGA, VHDL & Verilog lower case to upper case and vice versa


Author: Junior Hpc (Company: University) (junior_hpc)
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Hello.
I want to develop a VHDL application that given a text file, it converts 
all the lower case to upper case and vice versa. E.g., if the the input 
text is "Hello", then the VHDL should output "hELLO". The application 
passes the input text file stored on local machine to signal 
user_w_write_8_data which contains the characters of the input text 
file.
I don't know why, my VHDL code only convert one every two characters. 
E.g., if my input text is "Hello", my code outputs "HeLlO". I don't know 
whether it is a problem of clock cycle or something else. The algorithm 
should be ok, because the signal user_w_write_8_data contains the 8 bits 
of the character, e.g. "H" is represented in user_w_write_8_data as 
"01001000" and in order to convert "H" into "h" I only swap the fifth 
bit from 0 to 1 or from 1 to 0.

This is my VHDL code, do you have any idea where I am wrong?

Thanks.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity xillydemo is
  port (
     PCIE_PERST_B_LS : IN std_logic;
     PCIE_REFCLK_N : IN std_logic;
     PCIE_REFCLK_P : IN std_logic;
     PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
     PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
     GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
     PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
     PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
end xillydemo;

architecture sample_arch of xillydemo is
    signal tmp :  std_logic_vector(7 DOWNTO 0);
  

  component xillybus
    port (
      PCIE_PERST_B_LS : IN std_logic;
      PCIE_REFCLK_N : IN std_logic;
      PCIE_REFCLK_P : IN std_logic;
      PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
      PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
      GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
      PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
      PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
      bus_clk : OUT std_logic;
      quiesce : OUT std_logic;
      
      user_r_read_8_rden : OUT std_logic;
      user_r_read_8_empty : IN std_logic;
      user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
      user_r_read_8_eof : IN std_logic;
      user_r_read_8_open : OUT std_logic;
      user_w_write_8_wren : OUT std_logic;
      user_w_write_8_full : IN std_logic;
      user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
      user_w_write_8_open : OUT std_logic);
  end component;

  component fifo_8x2048
    port (
      clk: IN std_logic;
      srst: IN std_logic;
      din: IN std_logic_VECTOR(7 downto 0);
      wr_en: IN std_logic;
      rd_en: IN std_logic;
      dout: OUT std_logic_VECTOR(7 downto 0);
      full: OUT std_logic;
      empty: OUT std_logic);
  end component;


-- Synplicity black box declaration
  attribute syn_black_box : boolean;
  attribute syn_black_box of fifo_8x2048: component is true;
  
  signal bus_clk :  std_logic;
  signal quiesce : std_logic;

  signal reset_8 : std_logic;

  signal ram_addr : integer range 0 to 31;
 
  signal user_r_read_8_rden  :  std_logic;
  signal user_r_read_8_empty :  std_logic;
  signal user_r_read_8_data  :  std_logic_vector(7 DOWNTO 0);
  signal user_r_read_8_eof   :  std_logic;
  signal user_r_read_8_open  :  std_logic;
  signal user_w_write_8_wren :  std_logic;
  signal user_w_write_8_full :  std_logic;
  signal user_w_write_8_data :  std_logic_vector(7 DOWNTO 0);
  signal user_w_write_8_open :  std_logic;
  signal wr_en               :  std_logic := '0';
  signal din                 :  std_logic_vector(user_w_write_8_data'range) := (others => '0');

begin
  xillybus_ins : xillybus
    port map (
      -- Ports related to /dev/xillybus_read_8
      -- FPGA to CPU signals:
      user_r_read_8_rden => user_r_read_8_rden,
      user_r_read_8_empty => user_r_read_8_empty,
      user_r_read_8_data => user_r_read_8_data,
      user_r_read_8_eof => user_r_read_8_eof,
      user_r_read_8_open => user_r_read_8_open,

      -- Ports related to /dev/xillybus_write_8
      -- CPU to FPGA signals:
      user_w_write_8_wren => user_w_write_8_wren,
      user_w_write_8_full => user_w_write_8_full,
      user_w_write_8_data => user_w_write_8_data,
      user_w_write_8_open => user_w_write_8_open,

      -- General signals
      PCIE_PERST_B_LS => PCIE_PERST_B_LS,
      PCIE_REFCLK_N => PCIE_REFCLK_N,
      PCIE_REFCLK_P => PCIE_REFCLK_P,
      PCIE_RX_N => PCIE_RX_N,
      PCIE_RX_P => PCIE_RX_P,
      GPIO_LED => GPIO_LED,
      PCIE_TX_N => PCIE_TX_N,
      PCIE_TX_P => PCIE_TX_P,
      bus_clk => bus_clk,
      quiesce => quiesce
   );

  process (bus_clk)
  
  begin
  
     if (bus_clk'event and bus_clk = '1') then
        wr_en <= user_w_write_8_wren;
        if (user_w_write_8_wren = '1') then 
            din <= user_w_write_8_data;
            if (din(5)='1') then
                din(5)<='0';
            elsif (din(5)='0') then
                din(5)<='1';
            end if;
        end if;
     end if; 

  end process;

--  8-bit loopback

  fifo_8 : fifo_8x2048
    port map(
          clk        => bus_clk,
          srst       => reset_8,
          din        => din,
          wr_en      => wr_en,
          rd_en      => user_r_read_8_rden,
          dout       => user_r_read_8_data,
          full       => user_w_write_8_full,
          empty      => user_r_read_8_empty
      );

    reset_8 <= not (user_w_write_8_open or user_r_read_8_open);

    user_r_read_8_eof <= '0';
  
end sample_arch; 

Author: Ben (Guest)
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Hi,

the error occurs because you use synchronous pilelines of different 
lengths on the same data.

Your actions on the clock cycles for one date look like this:
1. user_w_write_8_wren = '1'
2. wr_en = '1', din = user_w_write_8_data
3. din(5) = not din(5), wr_en = '0'


This is such a trivial problem that you can easily do it in an 
asynchronous statement:
wr_en <= user_w_write_8_wren;
din <= user_w_write_8_data;
din(5) <= not user_w_write_8_data(5);

Author: Junior Hpc (Company: University) (junior_hpc)
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Wow it works... but I did not really understand why the following code 
did not work... The data is in the FIFO only when bus_clk'event and 
bus_clk = '1', isn't it?? Maybe I am wrong...
if (bus_clk'event and bus_clk = '1') then
   wr_en <= user_w_write_8_wren;
   din <= user_w_write_8_data;
   din(5) <= not user_w_write_8_data(5);
end if; 

Thanks.

Author: Ben (Guest)
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I have no idea why the code you posted should not work. It looks 
alright.

Author: Lattice User (Guest)
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Junior H. wrote:
> Wow it works... but I did not really understand why the following code
> did not work... The data is in the FIFO only when bus_clk'event and
> bus_clk = '1', isn't it?? Maybe I am wrong...
>
if (bus_clk'event and bus_clk = '1') then
   wr_en <= user_w_write_8_wren;
   din <= user_w_write_8_data;
   din(5) <= not user_w_write_8_data(5);
end if;
>

this is not your original code.

You original not working code ist equivalent to this:
if (bus_clk'event and bus_clk = '1') then
   wr_en <= user_w_write_8_wren;
   din <= user_w_write_8_data;
   din(5) <= not din(5);
end if;

which introduces an extra cycle delay only to bit 5.

Author: Lattice User (Guest)
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Lattice User wrote:
>
> which introduces an extra cycle delay only to bit 5.

Correction:
It just toggles bit 5 -> alternatnating lower and upper case.

Author: Junior Hpc (Company: University) (junior_hpc)
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Hello, I have some question about the following code line:
 din <= user_w_write_8_data; 

By reading xillybus documentation, user_w_write_8_data contains the data 
arriving from write_device_file but I don't understand what is din. 
Since the data output is represented by dout, how it is possible that by 
executing this line code:
 din <= user_w_write_8_data; 
the data goes into read_device_file?

Author: asdf (Guest)
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As you can see in the code, din is connected to the fifo write port, 
which is a buffer the component can read from.

There is no referecne in this thread about "read_device_file" and if you 
provide no context to your problem, no one will be able to help you with 
it.

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