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Forum: FPGA, VHDL & Verilog PLL use. Altera Quartus II v. 15.


Author: Alex Rybin (Company: None) (rybin87)
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Hello. I'm using Altera Quartus II v. 15, and I have created IP Altpll. 
It is not clear to me how to use it in the program. I'm asking for your 
help.

Author: Sym (Guest)
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Instantiate the component in your code and connect the clocks (and 
locked) signal. That's more or less all.
For simulation, you need the altera libraries (probably altera_mf and 
others).

Author: Alex Rybin (Company: None) (rybin87)
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Thank you!

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