Forum: FPGA, VHDL & Verilog How do I calculate average delay of inputs in iverilog.

Author: jake singh (Guest)
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I have built a 16 bit carry look ahead adder and randomized 5000 inputs 
I cant figure out how you would get an average delay of these inputs, 
also I am in structural iverilog.

Any help would be nice. i have added my testbench below

module testbench();
    wire [15:0] a,b,sum;
    wire cin,cout;
     testAdder test(a,b,sum,cout,cin);
     cla_16_two_level adder(sum,cout,a,b,cin);

    module testAdder(a,b,s,cout,cin);
    input [15:0] s;
    input cout;
    output [15:0] a,b;
    output cin;
    reg [15:0] a,b;
    reg cin;
    integer i;
    integer seed =16;
    integer f;
    initial begin
    $monitor($time,"a=%d, b=%d, cin=%b, s=%d, cout=%b",a,b,cin,s,cout);
     for(i=0; i<5000; i=i+1) begin
              a = $random(seed);
              b = $random(seed);
              cin = $random(seed);



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