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Forum: FPGA, VHDL & Verilog How to port map selected signals from a large vector to smaller one


Author: Rohan Narkhede (Guest)
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Hi,

I need a help.

I want to map a input port of D flip flop (named 'din') which is 
STD_LOGIC_VECTOR(7 downto 0) with the internal signal sumf : 
STD_LOGIC_VECTOR (24 downto 0) such that I want to map elements 
23,22,21,20,15,14,13,12,7...to 0 of sumf to port din.


I write the code :

din=>(sumf(23 downto 20, 15 downto 12, 7 downto 0)).

I get an error "Sliced name is allowed only on single dimensional 
array". What is the procedure to port map selected elements in vector to 
other vector as in this case?

Thanks and regards,
Rohan Narkhede

Author: Rohan Narkhede (Guest)
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Sorry, I mean to say din is of of size 16:

din : in STD_LOGIC_VECTOR (15 downto 0);

Author: nerved (Guest)
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Rohan Narkhede wrote:
> I write the code :
>
> din=>(sumf(23 downto 20, 15 downto 12, 7 downto 0)).

while din is std_logic_vector (7 downto 0) is only 8 Bit wide, you cant 
put in 16 Bits!

Either you define din as std_logic_vector (15 downto 0) and try this:

[code] din <= sumf(23 downto 20) & sumf(15 downto 12) & sumf(7 downto 
0);

Or you have to serialize the signal an feed in two cycles.

Author: nerved (Guest)
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Rohan Narkhede wrote:
> Sorry, I mean to say din is of of size 16:
>
> din : in STD_LOGIC_VECTOR (15 downto 0);

Sorry, i didnt read yout secon post...

I think, this should work:
 din <= sumf(23 downto 20) & sumf(15 downto 12) & sumf(7 downto 
0);

Author: Lothar Miller (lkmiller) (Moderator)
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Rohan Narkhede wrote:
> What is the procedure to port map selected elements in vector to other
> vector as in this case?
The keyword here is the concatenation operator "&"
Have a very, very close look what it does. Its a very essential operator 
in VHDL. Its the "glue" that puts bits to vectors, and parts of vectors 
to longer vectors...

: Edited by Moderator

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